Speculative hybrid branch direction predictor

Abstract

An apparatus for speculatively predicting the direction of a branch instruction in a pipelined microprocessor in a hybrid fashion. A branch target address cache (BTAC) stores a direction prediction about executed branch instructions. The BTAC is indexed by an instruction cache fetch address. The BTAC is accessed in parallel with the instruction cache access, such that the direction prediction is provided before the actual instruction is decoded which is presumed to be a branch instruction corresponding to the direction prediction stored in the BTAC. In parallel with the BTAC access, a branch history table (BHT) is accessed to provide a second speculative direction prediction. The BHT is indexed with a gshare function of the instruction cache fetch address and a global branch history stored in a global branch history register. The BTAC also provides a selector that selects between the two speculative direction predictions.

1 - 36 . (canceled)  
   
   
       37 . A method for speculatively branching in a microprocessor, the method comprising: 
 generating a plurality of speculative branch direction predictions of an instruction;    selecting one of said plurality of speculative branch direction predictions as a final direction prediction; and    speculatively branching the microprocessor if said final direction prediction indicates said instruction will be taken;    wherein said generating, said selecting, and said speculatively branching are preformed prior to decoding said instruction.    
   
   
       38 . The method of  claim 37 , further comprising: 
 detecting said final direction erroneously indicated said instruction will be taken subsequent to said speculatively branching.    
   
   
       39 . The method of  claim 38 , further comprising: 
 branching to a correct target address in response to said detecting.    
   
   
       40 - 45 . (canceled)