Flash memory device and flash memory system including buffer memory

Abstract

A flash memory device includes a flash memory and a buffer memory. The flash memory is divided into a main region and a spare region. The buffer memory is a random access memory and has the same structure as the flash memory. In addition, the flash memory device further includes control means for mapping an address of the flash memory applied from a host so as to divide a structure of the buffer memory into a main region and a spare region and for controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.

1 . A flash memory device comprising: 
 a flash memory divided into a flash main region and a flash spare region;    a buffer memory to temporarily store data to be written to the flash memory or data to be read from the flash memory, the buffer memory being divided into a buffer main region and a buffer spare region so as to have a same address structure as the flash memory; and    control means to map an address of the flash memory applied from a host to be suitable for the buffer memory and controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.    
   
   
       2 . The flash memory device of  claim 1 , wherein the flash memory, the buffer memory and the control means are structured on one chip.  
   
   
       3 . The flash memory device of  claim 1 , further including a host interface to change a control signal, an address, and data, which are applied from the host, into an internal signal to operate the flash memory device.  
   
   
       4 . The flash memory device of  claim 1 , wherein the buffer memory is a random access memory.  
   
   
       5 . The flash memory device of  claim 4 , wherein the random access memory is a SRAM.  
   
   
       6 . The flash memory device of  claim 4 , wherein the random access memory is a DRAM.  
   
   
       7 . The flash memory device of  claim 1 , wherein the control means comprises: 
 a register to store an address of the flash memory, an address of the buffer memory and a command;    a buffer controller to control read and write operations of the buffer memory;    a flash controller to control read and write operations of the flash memory; and    a state machine to control the buffer controller and the flash controller so as to store data of the buffer memory in the flash memory or store data of the flash memory in the buffer memory according to values stored in the register.    
   
   
       8 . The flash memory device of  claim 7 , wherein the control means further includes an error correction and data input/output circuit, and 
 wherein the error correction and data input/output circuit is controlled by the state machine and corrects an error of data transmitted between the buffer memory and the flash memory.    
   
   
       9 . The flash memory device of  claim 7 , wherein the control means further includes a decoder to map an address applied from the buffer controller.  
   
   
       10 . The flash memory device of  claim 9 , wherein the decoder separates an address input to the buffer memory into the buffer main region and the buffer spare region.  
   
   
       11 . A flash memory system comprising: 
 a host; and    a flash memory device to store data or output stored data according to a request of the host, wherein the flash memory device includes a flash memory divided into a flash main region and a flash spare region, a buffer memory to temporarily store data to be written in the flash memory or data to be read from the flash memory, the buffer memory being divided into a buffer main region and a buffer spare region so as to have a same address structure as the flash memory, and a control means to map an address of the flash memory applied from the host to be suitable to the buffer memory and controlling the flash memory and the buffer memory to store data of the buffer memory in the flash memory or to store data of the flash memory in the buffer memory.    
   
   
       12 . The flash memory system of  claim 11 , wherein the flash memory, the buffer memory, and the control means are structured on one chip, respectively.  
   
   
       13 . The flash memory system of  claim 11 , further including a host interface to change a control signal, an address, and the data, which are applied from the host into an internal signal to operate the flash memory device.  
   
   
       14 . The flash memory system of  claim 11 , wherein the buffer memory is a random access memory.  
   
   
       15 . The flash memory system of  claim 14 , wherein the random access memory is a SRAM.  
   
   
       16 . The flash memory system of  claim 14 , wherein the random access memory is a DRAM.  
   
   
       17 . The flash memory system of  claim 11 , wherein the control means comprises: 
 a register to store an address of the flash memory, an address of the buffer memory, and a command;    a buffer controller to control read and write operations of the buffer memory;    a flash controller to control read and write operations of the flash memory; and    a state machine to control the buffer controller and the flash controller so as to respectively store data of the buffer memory in the flash memory or store data of the flash memory in the buffer memory according to values stored in the register.    
   
   
       18 . The flash memory system of  claim 17 , wherein the control means further includes an error correction and data input/output circuit, and 
 wherein the error correction and data input/output circuit is controlled by the state machine and corrects an error of data transmitted between the buffer memory and the flash memory.    
   
   
       19 . The flash memory system of  claim 17 , wherein the control means further includes a decoder to map an address applied from the buffer controller.  
   
   
       20 . The flash memory system of  claim 19 , wherein the decoder separates an address input to the buffer memory into a buffer main region and a buffer spare region.