Non volatile memory and data processor

Abstract

The present invention aims to shorten the time required to charge and discharge a bit line connected with each of non-volatile memory cells and speed up the reading of memory information from the non-volatile memory cell. With a main/sub bit line structure as a premise, a clamp voltage is supplied from each of voltage supply elements (QPC 0 through QPCm) to each of main bit lines (MB 0 through MBm). during a period prior to and subsequent to a read operation for a non-volatile memory cell (MC). In parallel with it, sub bit lines (LB 00 through LBkm) are respectively discharged by discharge elements (QD 00 through QDkm). There is no need to precharge the main bit line from a ground level upon the operation of reading memory information and a read operation time can hence be shortened. Thus, a non-volatile memory becomes fast in operating speed. Since the drain (sub bit line) of the memory cell is maintained at a ground potential, no memory disturb problem arises.

1 - 23 . (canceled)  
   
   
       24 . A nonvolatile memory apparatus adapted to performing a data read operation, comprising: 
 a bit line coupled to a sub bit line via a first switch circuit;    a word line;    a nonvolatile memory cell coupled to said sub bit line and said word line;    a sense amplifier coupled to said bit line; and    a power circuit,    wherein said nonvolatile memory cell is capable of storing data, and has a threshold voltage within an arbitrary one of a plurality of threshold voltage ranges corresponding to data stored therein,    wherein in a data read operation, said first switch circuit is turned on, said power circuit charges a first voltage to said bit line and said sub bit line, charges a read voltage to said word line after charging said first voltage, and then said sense amplifier senses a voltage level of said bit line to detect whether the voltage level of said bit line is lower than said first voltage or higher than said first voltage, and    wherein said power circuit causes the voltage level of said bit line to move to a second voltage after the sensing by said sense amplifier, and the voltage level of said bit line remains at said second voltage after completion of said data read operation.    
   
   
       25 . A nonvolatile memory apparatus according to  claim 24 , 
 wherein said power circuit charges said bit line to said second voltage when the voltage level of said bit line is lower than said second voltage after the sensing by said sense amplifier, and    wherein said power circuit discharges said bit line to said second voltage when the voltage level of said bit line is higher than said second voltage after the sensing by said sense amplifier.    
   
   
       26 . A nonvolatile memory apparatus according to  claim 25 , 
 wherein said first switch circuit is turned off after the sensing by said sense amplifier, and then a voltage level of said sub bit line is caused to move to a third voltage lower than said first voltage and said second voltage.    
   
   
       27 . A nonvolatile memory apparatus according to  claim 26 , further comprising: 
 a second bit line coupled to a second sub bit line via a second switch circuit;    a second nonvolatile memory cell coupled to said second sub bit line and said word line; and    a second sense amplifier coupled to said second bit line,    wherein in said data read operation, said second switch circuit is turned on, said power circuit charges said first voltage to said second bit line and said second sub bit line, charges said read voltage to said word line after charging said first voltage, and then said second sense amplifier senses a voltage level of said second bit line to detect whether the voltage level of said second bit line is lower than said first voltage or higher than said first voltage, and    wherein said power circuit causes the voltage level of said second bit line to move to said second voltage after the sensing by said second sense amplifier, and the voltage level of said second bit line remains at said second voltage after completion of said data read operation.    
   
   
       28 . A nonvolatile memory apparatus according to  claim 27 , further being adapted to performing a data write operation and a data erase operation, 
 wherein in said data write operation, the threshold voltage of one of said nonvolatile memory cells to be written is moved into one of said plurality of threshold voltage ranges corresponding to data to be stored therein,    wherein in said data erase operation, the threshold voltage of one of said nonvolatile memory cells to be erased is moved into a threshold voltage range of said plurality of threshold voltage ranges corresponding to an erase state, and    wherein before moving of the threshold voltage of the respective nonvolatile memory cell in each of said data write operation and said data erase operation, said power circuit causes the voltage levels of said bit line and said second bit line move to said third voltage.    
   
   
       29 . A nonvolatile memory apparatus according to  claim 28 , 
 wherein said first voltage is near to a level of said second voltage, and    wherein said third voltage is a ground voltage.    
   
   
       30 . A nonvolatile memory apparatus according to  claim 24 , 
 wherein said nonvolatile memory cell has a gate terminal, a first semiconductor region, a second semiconductor region, and a floating gate,    wherein said gate terminal of said nonvolatile memory cell is coupled to said word line,    wherein said first semiconductor region is coupled to said sub bit line,    wherein said second semiconductor region is coupled to a source line, and    wherein electrons can be injected into and ejected from said floating gate.