Multi-die processor

Abstract

Disclosed are a multi-die processor apparatus and system. Processor logic to execute one or more instructions is allocated among two or more face-to-faces stacked dice. The processor includes a conductive interface between the stacked dice to facilitate die-to-die communication.

1 . An apparatus comprising: 
 a first die having a first face side and a first back side, the first die comprising a first logic portion;    a second die having a second face side and a second back side, the second die comprising a second logic portion;    said first and second dice being coupled together with their faces opposed to each other;    wherein said first logic portion and said second logic portion are to cooperatively execute an instruction.    
   
   
       2 . The apparatus of  claim 1 , wherein 
 said first and second dice are further coupled such that the first logic portion and said second logic portion at least partially overlap.    
   
   
       3 . The apparatus of  claim 1 , wherein: 
 to cooperatively execute an instruction is further to cooperatively accomplish sub-instruction level tasks in response to an instruction.    
   
   
       4 . The apparatus of  claim 1 , further comprising: 
 a conductive inter-die interface between the opposing faces of the first and second dice.    
   
   
       5 . The apparatus of  claim 4 , wherein: 
 the inter-die interface is disposed between a subset of the face side of the first die and a subset of the face side of the second die.    
   
   
       6 . The apparatus of  claim 5 , wherein: 
 the subset of the face side of the first die is a central region.    
   
   
       7 . The apparatus of  claim 5 , wherein: 
 the subset of the face side of the second die is a central region.    
   
   
       8 . The apparatus of  claim 5 , wherein: 
 the subset of the face side of the first die is a perimeter region.    
   
   
       9 . The apparatus of  claim 5 , wherein: 
 the subset of the face side of the second die is a perimeter region.    
   
   
       10 . The apparatus of  claim 4 , further comprising: 
 an interface portion, said interface portion being operatively coupled to at least one of said first logic portion and said second logic portion to generate inter-component signals between the processor and a component.    
   
   
       11 . The apparatus of  claim 10 , wherein: the interface portion is coupled to the first die.  
   
   
       12 . The apparatus of  claim 10 , wherein: 
 the component is a memory system.    
   
   
       13 . The apparatus of  claim 1 , wherein: 
 said first logic portion and said second logic portion collectively form address generation logic.    
   
   
       14 . The apparatus of  claim 1 , wherein: 
 said first logic portion and said second logic portion collectively form scheduling logic.    
   
   
       15 . The apparatus of  claim 14 , wherein: 
 said first logic portion comprises arithmetic scheduling logic and wherein said second logic portion comprises memory request scheduling logic.    
   
   
       16 . The apparatus of  claim 1 , wherein: 
 said first logic portion comprises a first portion of an array and wherein said second logic portion comprises a second portion of the array.    
   
   
       17 . The apparatus of  claim 16 , wherein: 
 wherein said array is a register file array.    
   
   
       18 . The apparatus of  claim 16 , wherein: 
 said array is a microcode memory array.    
   
   
       19 . The apparatus of  claim 1 , wherein 
 said first logic portion comprises a hot logic block and said second logic portion comprises a cool logic block.    
   
   
       20 . The apparatus of  claim 19 , wherein 
 said first logic portion at least partially overlaps said second logic portion.    
   
   
       21 . The apparatus of  claim 19 , wherein: 
 said first logic portion further comprises an execution unit and wherein said second logic portion further comprises a data cache.    
   
   
       22 . The apparatus of  claim 1 , wherein: 
 said first logic portion comprises a first execution unit and said second logic portion comprises a second execution unit.    
   
   
       23 . The apparatus of  claim 22 , wherein: 
 said first execution unit comprises an integer execution unit and said second execution unit comprises a floating point execution unit.    
   
   
       24 . The apparatus of  claim 22 , wherein: 
 said first execution unit comprises floating point execution unit and said second execution unit comprises a single-instruction-multiple-data (SIMD) execution unit    
   
   
       25 . The apparatus of  claim 1 , wherein: 
 the first logic portion is disposed on the face side of the first die.    
   
   
       26 . The apparatus of  claim 1 , wherein: 
 the second logic portion is disposed on the face side of the second die.    
   
   
       27 . The apparatus of  claim 1 , wherein: 
 said first logic portion comprises logic to execute a first pipeline stage to execute the instruction; and    said second logic portion comprises logic to execute a second pipeline stage to execute the instruction.    
   
   
       28 . The apparatus of  claim 27 , wherein: 
 logic blocks for additional pipeline stages are disposed on said first and second dice such that a signal path for the pipeline follows a zigzag path between the first and second dice.    
   
   
       29 . A processor comprising: 
 a first partition on a first die;    a second partition on a second die; and    execution logic to invoke the first partition and the second partition to perform an execution operation associated with an instruction.    
   
   
       30 . The processor of  claim 29 , wherein: 
 said execution operation further comprises a scheduling operation.    
   
   
       31 . The processor of  claim 29 , wherein: 
 said execution operation further comprises an address generation operation.    
   
   
       32 . The processor of  claim 29 , wherein: 
 said execution logic, in response the instruction, is further to invoke a partition on the first die to invoke a second execution operation associated with the instruction and is to invoke a partition on the second die to perform a third execution operation associated with the instruction.    
   
   
       33 . The processor of  claim 32 , wherein: 
 said second execution operation further comprises an operation associated with an execute stage of an instruction pipeline.    
   
   
       34 . The processor of  claim 32 , wherein: 
 said second execution operation further comprises an instruction pointer generation operation.    
   
   
       35 . The processor of  claim 29 , wherein: 
 said execution operation further comprises an instruction fetching operation.    
   
   
       36 . The processor of  claim 29 , wherein: 
 said second execution operation further comprises a decoding operation.    
   
   
       37 . The processor of  claim 29 , wherein: 
 said second execution operation further comprises a renaming operation.    
   
   
       38 . The processor of  claim 29 , wherein: 
 said second execution operation further comprises a retirement operation.    
   
   
       39 . An apparatus, comprising: 
 a first die comprising: 
 an execution unit; and  
 a first array fraction; and  
   a second die comprising: 
 a second array fraction coupled to said first register file fraction by die-to-die couplings to cooperatively operate as an array in conjunction with said first array fraction.  
   
   
   
       40 . The apparatus of  claim 39 , wherein: 
 said first die further comprises a first scheduling fraction; and    said second die further comprises a second scheduling fraction coupled to said first scheduling fraction by die-to-die couplings to cooperatively operate as a scheduling unit in conjunction with said first scheduling fraction.    
   
   
       41 . The apparatus of  claim 39 , wherein: 
 said first die further comprises a first address generation fraction; and    said second die further comprises a second address generation fraction;    wherein said first address generation fraction is coupled to said second address generation fraction to cooperatively operate as an address generation unit in conjunction with the second address generation fraction.    
   
   
       42 . The apparatus of  claim 39 , wherein: 
 the array is a register file.    
   
   
       43 . The apparatus of  claim 39 , wherein: 
 the array is a microcode memory array.    
   
   
       44 . The apparatus of  claim 39 , wherein a microprocessor comprises said first die comprising said first partition and said second die comprising said second partition as well as an interface disposed on said first die, and further wherein said apparatus is a system further comprising: 
 a memory coupled to the interface portion of the microprocessor, said memory to store an instruction which when executed by the microprocessor causes said microprocessor to invoke said first partition on said first die and said second partition on said second die    
   
   
       45 . The system of  claim 38 , further comprising: 
 an additional system component comprising an RF unit.    
   
   
       46 . The apparatus of  claim 1 , wherein 
 said first logic portion comprises a low power-density region and said second logic portion comprises a high power-density region.    
   
   
       47 . The apparatus of  claim 46 , wherein 
 said first logic portion at least partially overlaps said second logic portion.