Chip-scale package and carrier for use therewith

Abstract

A carrier for use in a chip-scale package includes a film with at least one aperture defined therethrough. The aperture, which is alignable with a corresponding bond pad of a semiconductor device over which the carrier is to be positioned, is at least partially filled with conductive material. A contact on a surface of the carrier may communicate with the conductive material within the aperture. A conductive bump may be disposed adjacent the contact. The carrier may be positioned on a semiconductor device to form a chip-scale package. Such a chip-scale package may include a semiconductor device invertedly disposed over the carrier with bond pads of the semiconductor device being substantially aligned with apertures of the carrier.

1 . A carrier for use in a chip-scale package, comprising: 
 a preformed film, the preformed film including a first surface configured to be disposed in substantial contact with an active surface of a semiconductor device;    at least one conductive via extending substantially longitudinally through the preformed film prior to placement thereof upon the active surface of the semiconductor device, electrically exposed at the first surface of the preformed polymeric film; and    at least one contact at a second surface of the preformed film and in communication with the at least one conductive via, and the at least one contact and the at least one conductive via being positioned to align with at least one bond pad of the semiconductor device.    
     
     
         2 . The carrier of  claim 1 , wherein the preformed film comprises a polymer.  
     
     
         3 . The carrier of  claim 1 , wherein the at least one conductive via comprises a conductive bump.  
     
     
         4 . The carrier of  claim 3 , wherein the conductive bump comprises solder.  
     
     
         5 . The carrier of  claim 3 , wherein the conductive bump also forms the at least one contact.  
     
     
         6 . The carrier of  claim 5 , wherein the conductive bump comprises solder.  
     
     
         7 . The carrier of  claim 1 , further comprising: 
 at least another conductive via extending substantially through the preformed film and corresponding to at least another bond pad of the semiconductor device; and    at least another contact corresponding to the at least another conductive via at the second surface of the preformed film and positioned to align with the at least another bond pad of the semiconductor device.    
     
     
         8 . The carrier of  claim 7 , wherein the at least another conductive via is laterally offset relative to the at least another bond pad.  
     
     
         9 . The carrier of  claim 7 , further comprising: 
 at least one conductive trace extending laterally between the at least another conductive via and the at least another contact.    
     
     
         10 . The carrier of  claim 1 , wherein the at least one conductive via is configured to directly contact the at least one bond pad.  
     
     
         11 . A chip-scale package, comprising: 
 a carrier including at least one aperture extending substantially longitudinally therethrough; and    a semiconductor device including an active surface having at least one bond pad thereon, the at least one bond pad electrically exposed through the carrier by way of the at least one aperture, an active surface-abutting surface of the carrier in substantial contact with the active surface and secured thereto with adhesive material disposed between the carrier and the active surface.    
     
     
         12 . The chip-scale package of  claim 11 , wherein the at least one aperture and the at least one bond pad are substantially aligned.  
     
     
         13 . The chip-scale package of  claim 11 , further comprising: 
 conductive material within the at least one aperture.    
     
     
         14 . The chip-scale package of  claim 13 , wherein the conductive material communicates with the at least one bond pad.  
     
     
         15 . The chip-scale package of  claim 13 , wherein the conductive material contacts the at least one bond pad.  
     
     
         16 . The chip-scale package of  claim 15 , wherein the conductive material comprises solder.  
     
     
         17 . The chip-scale package of  claim 15 , wherein the conductive material forms a conductive bump.  
     
     
         18 . The chip-scale package of  claim 15 , wherein the conductive material forms a contact.  
     
     
         19 . The chip-scale package of  claim 15 , further comprising a conductive elastomer disposed over the conductive material.  
     
     
         20 . The chip-scale package of  claim 19 , further comprising at least one conductive bump disposed on the conductive elastomer, opposite the conductive material, and in communication therewith.  
     
     
         21 . The chip-scale package of  claim 13 , further comprising: 
 a contact located over the at least one aperture and in communication with the conductive material therein.    
     
     
         22 . The chip-scale package of  claim 21 , further comprising: 
 a conductive structure secured to the contact.    
     
     
         23 . The chip-scale package of  claim 22 , wherein the conductive structure comprises a conductive bump.  
     
     
         24 . The chip-scale package of  claim 23 , wherein the conductive bump comprises solder.  
     
     
         25 . The chip-scale package of  claim 11 , wherein the carrier comprises a polymeric carrier.  
     
     
         26 . The chip-scale package of  claim 11 , wherein the carrier at least partially contacts a peripheral edge of the semiconductor device.