Semiconductor device and method of fabricating the same

Abstract

A semiconductor device includes a semiconductor substrate of a first conduction type, a first well of a second conduction type formed on the semiconductor substrate, a plurality of second wells of the first conduction type provided in the first well for forming memory cells and a peripheral circuit respectively, each second well having a first depth, a first trench isolating region formed so as to isolate an element within the second well for the memory cells and having a first depth, a guard-ring diffusion region of the first conduction type provided in the vicinity of a peripheral edge of each second well for the memory cells and doped with a high density impurity so as to encompass a forming region of the memory cells, a second trench isolating region formed so that a p-n junction of each second well terminates on a bottom thereof in the vicinity of an outside of the guard-ring diffusion region, the second trench isolating region having a second depth larger than the first depth of each second well, and a third trench isolating region isolating an element formed in each second well for the peripheral circuit, the third trench isolating region having the second depth.

1 . A semiconductor device comprising: 
 a semiconductor substrate of a first conduction type;    a first well of a second conduction type formed on the semiconductor substrate;    a plurality of second wells of the first conduction type provided in the first well for forming memory cells and a peripheral circuit respectively, each second well having a first depth;    a first trench isolating region formed so as to isolate an element within the second well for the memory cells and having a first depth;    a guard-ring diffusion region of the first conduction type provided in the vicinity of a peripheral edge of each second well for the memory cells and doped with a high density impurity so as to encompass a forming region of the memory cells;    a second trench isolating region formed so that a p-n junction of each second well terminates on a bottom thereof in the vicinity of an outside of the guard-ring diffusion region, the second trench isolating region having a second depth larger than the first depth of each second well; and    a third trench isolating region isolating an element formed in each second well for the peripheral circuit, the third trench isolating region having the second depth.    
   
   
       2 . The semiconductor device according to  claim 1 , wherein the guard-ring diffusion region has a diffusion depth set to be larger than the first depth of the first trench isolating region and smaller than the second depth of the second trench isolating region.  
   
   
       3 . The semiconductor device according to  claim 1 , wherein the first depth of the first trench isolating region is set to be larger than a diffusion depth of high density impurity diffusion region of a second conduction type to be formed as an element within the second well for the memory cells and smaller than a diffusion depth of high density impurity diffusion region of the second conduction type to be formed as an element within the second well for the peripheral circuit, and the second depth of the second and third trench isolating regions is set to be smaller than a diffusion depth of high density impurity diffusion region of the first conduction type within the second well for the peripheral circuit.  
   
   
       4 . The semiconductor device according to  claim 2 , wherein the first depth of the first trench isolating region is set to be larger than a diffusion depth of high density impurity diffusion region of a second conduction type to be formed as an element within the second well for the memory cells and smaller than a diffusion depth of high density impurity diffusion region of a second conduction type to be formed as an element within the second well for the peripheral circuit, and the second depth of the second and third trench isolating regions is set to be smaller than a diffusion depth of high density impurity diffusion region of a first conduction type within the second well for the peripheral circuit.  
   
   
       5 . The semiconductor device according to  claim 1 , wherein an element constituting the memory cell is provided with a gate dielectric film with a first film thickness, and an element constituting the peripheral circuit is provided with a gate dielectric film with a second film thickness larger than the first film thickness.  
   
   
       6 . The semiconductor device according to  claim 2 , wherein an element constituting each memory cell is provided with a gate dielectric film with a first film thickness, and an element constituting the peripheral circuit is provided with a gate dielectric film with a second film thickness larger than the first film thickness.  
   
   
       7 . The semiconductor device according to  claim 3 , wherein an element constituting each memory cell is provided with a gate dielectric film with a first film thickness, and an element constituting the peripheral circuit is provided with a gate dielectric film with a second film thickness larger than the first film thickness.  
   
   
       8 . The semiconductor device according to  claim 5 , wherein the gate dielectric film with the second film thickness is formed in a boundary region between the guard-ring diffusion region of the second well for the memory cells and the element forming region side.  
   
   
       9 . The semiconductor device according to  claim 5 , further comprising a low withstand pressure region formed with a gate dielectric film with a third film thickness smaller than the first film thickness and a guard-ring diffusion region of the first conduction type for a peripheral circuit, formed so as to encompass the low withstand pressure region and doped with a high density impurity, wherein the guard-ring diffusion region for the peripheral circuit is formed in a region formed with the second gate dielectric film.  
   
   
       10 . The semiconductor device according to  claim 8 , further comprising a low withstand pressure region formed with a gate dielectric film with a third film thickness smaller than the first film thickness and a guard-ring diffusion region of the first conduction type for a peripheral circuit, formed so as to encompass the low withstand pressure region and doped with a high density impurity, wherein the guard-ring diffusion region for the peripheral circuit is formed in a region formed with the second gate dielectric film.  
   
   
       11 . A method of fabricating a semiconductor device, comprising: 
 forming a first well of a second conduction type and a second well of a first conduction type on a semiconductor substrate of the first conduction type;    forming a gate oxide corresponding to each element on a surface of the semiconductor substrate;    forming trenches by etching at forming locations of first and second trench isolating regions respectively at a first depth larger than a depth of a diffusion layer formed in a memory-cell forming region within the second well and smaller than a depth of a diffusion layer of a transistor of a peripheral circuit region;    executing additional etching at a forming location of the second trench isolating region so that a second depth larger than the first depth is obtained; and    doping the trenches at the forming locations of the first and second trench isolating regions respectively, with a doping agent, thereby executing a planarization process.    
   
   
       12 . The method according to  claim 11 , wherein the gate dielectric film forming step includes a step of forming a gate dielectric film having a first film thickness corresponding to a transistor of the memory-cell forming region and a step of forming a gate dielectric film having a second film thickness corresponding to a transistor of the peripheral circuit region.  
   
   
       13 . The method according to  claim 11 , wherein in the gate dielectric film forming step, the gate dielectric film having the second film thickness is formed on a surface of a guard-ring diffusion region formed around the memory-cell forming region within the second well.  
   
   
       14 . The method according to  claim 12 , wherein in the gate dielectric film forming step, the gate dielectric film having the second film thickness is formed on a surface of a guard-ring diffusion region formed around the memory-cell forming region within the second well.