Image sensor applied with device isolation technique for reducing dark signals and fabrication method thereof

Abstract

The present invention relates to an image sensor applied with a device isolation technique for reducing dark signals and a fabrication method thereof. The image sensor includes: a logic unit; and a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.

1 . An image sensor, comprising: 
 a logic unit; and    a light collection unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.    
     
     
         2 . The image sensor as recited in  claim 1 , wherein the substrate and the field ion-implantation region are formed of a first conductive type and the photodiode is formed of a second conductive type.  
     
     
         3 . The image sensor as recited in  claim 1 , wherein the insulation layer is an oxide layer grown by a thermal process.  
     
     
         4 . The image sensor as recited in  claim 1 , wherein the logic unit includes an insulation layer for device isolation formed by a local oxidation of silicon (LOCOS) technique and a shallow trench isolation (STI) technique.  
     
     
         5 . A complementary metal oxide semiconductor (CMOS) image sensor, comprising: 
 a logic unit; and    a pixel array unit in which a plurality of photodiodes is formed, wherein the photodiodes are isolated from each other by a field ion-implantation region formed under a surface of a substrate and an insulation layer formed on the surface of the substrate.    
     
     
         6 . The CMOS image sensor as recited in  claim 5 , wherein the substrate and the field ion-implantation region are formed of a first conductive type and the photodiode is formed of a second conductive type.  
     
     
         7 . The CMOS image sensor as recited in  claim 5 , wherein the logic unit includes an insulation layer for device isolation formed by one of a LOCOS technique and a STI technique.  
     
     
         8 . The CMOS image sensor as recited in  claim 5 , wherein the insulation layer is an oxide layer grown by a thermal process.  
     
     
         9 . The CMOS image sensor as recited in  claim 5 , wherein the insulation layer is formed with a predetermined thickness in consideration of ion-implantation energy used in a subsequent ion-implantation process.  
     
     
         10 . A method for forming a device isolation structure in an image sensor including a light collection unit and a logic unit, comprising the steps of: 
 forming an insulation layer pattern on a substrate in a field region of the light collection unit;    forming an insulation layer for device isolation in a field region of the logic unit by performing one of a LOCOS technique and a STI technique; and    forming a field ion-implantation region under a surface of the substrate in the field region of the light collection unit.    
     
     
         11 . The method as recited in  claim 10 , wherein the insulation layer pattern is formed in a manner to have inclined sidewalls.  
     
     
         12 . The method as recited in  claim 10 , wherein the step of forming the insulation layer pattern includes the steps of: 
 stacking an oxide layer and a nitride layer on a substrate;    forming a mask pattern on the nitride layer, the mask pattern opening an active region of the light collection unit;    performing a dry etching process and a subsequent wet etching process to the nitride layer and the oxide layer by using the mask pattern as an etch mask; and    removing the mask pattern and the nitride layer.    
     
     
         13 . The method as recited in  claim 10 , wherein an undercut is formed at a bottom portion of each sidewall of the nitride layer patterned by the dry etching process.  
     
     
         14 . The method as recited in  claim 10 , wherein the oxide layer is made to remain in a thickness ranging from about 600 Å to about 700 Å during the dry etching process.  
     
     
         15 . The method as recited in  claim 12 , wherein the oxide layer is grown by a thermal process.