Semiconductor device

Abstract

A semiconductor device comprises n-type and p-type semiconductor devices formed on the substrate, the n-type device including an n-channel region formed on the substrate, n-type source and drain regions formed opposite to each other interposing the n-channel region therebetween, a first gate insulator formed on the n-channel region, and a first gate electrode formed on the first gate insulator and including a compound of a metal M and a first group-IV elements Si 1−a Ge a (0≦a≦1), the p-type device including a p-channel region formed on the substrate, p-type source and drain regions formed opposite to each other interposing the p-channel region therebetween, a second gate insulator formed on the p-channel region, and a second gate electrode formed on the second gate insulator, and including a compound of the metal M and a second group-IV element Si 1−c Ge c (0≦c≦1, a≠c).

1 . A semiconductor device comprising: 
 a silicon substrate;    an n-type semiconductor device and a p-type semiconductor device, each being formed on the silicon substrate,    the n-type semiconductor device including:    an n-channel region formed on a surface of the silicon substrate;    an n-type source region and an n-type drain region formed opposite to each other on a surface of the silicon substrate interposing the n-channel region therebetween;    a first gate insulator formed on the surface of the n-channel region between the n-type source region and the n-type drain region; and    a first gate electrode formed on the first gate insulator, and including a compound of a metal element M and a first group-IV semiconductor element Si 1−a  Ge a , where 0≦a≦1,    the p-type semiconductor device including:    a p-channel region formed on a surface of the silicon substrate;    a p-type source region and a p-type drain region formed opposite to each other on a surface of the silicon substrate interposing the p-channel region therebetween;    a second gate insulator formed on the surface of the p-channel region between the p-type source region and the p-type drain region; and    a second gate electrode formed on the second gate insulator, and including a compound of the metal element M and a second group-IV semiconductor element Si 1−c  Ge c , where 0≦c≦1, a≠c.    
   
   
       2 . The device according to  claim 1 , wherein the metal element M includes one selected from the group consisting of Ni, Pd, Pt, Ta, Er, Ti and Zr.  
   
   
       3 . The device according to  claim 1 , wherein the device satisfies conditions a≦0.3 and c≦0.3.  
   
   
       4 . The device according to  claim 1 , wherein the metal element M is Ni, and satisfies a condition c>a.  
   
   
       5 . The device according to  claim 1 , wherein the metal element M includes two or more metal elements selected from the group consisting of Ni, Pd and Pt or includes Ti and Zr.  
   
   
       6 . The device according to  claim 1 , wherein at least one of the first gate electrode and the second gate electrode includes one selected from the group consisting of As, P and B.  
   
   
       7 . The device according to  claim 1 , wherein the p-type semiconductor device and the n-type semiconductor device are configured to be fully depleted.  
   
   
       8 . The device according to  claim 1 , wherein the p-type semiconductor device and the n-type semiconductor device form a complementary pair.  
   
   
       9 . The device according to  claim 1 , wherein the first gate electrode and the second gate electrode include B, and the first gate electrode satisfies a condition a≠0 while the second gate electrode satisfies a condition c=0.  
   
   
       10 . The device according to  claim 1 , wherein Ge included in the first gate electrode is more than 5% with respect to Si.  
   
   
       11 . A semiconductor device comprising: 
 a silicon substrate;    an n-type semiconductor device and a p-type semiconductor device, each being formed on the silicon substrate,    the n-type semiconductor device including:    an n-channel region formed on a surface of the silicon substrate;    an n-type source region and an n-type drain region formed opposite to each other on a surface of the silicon substrate interposing the n-channel region therebetween;    a first gate insulator formed on the surface of the n-channel region between the n-type source region and the n-type drain region; and    a first gate electrode formed on the first gate insulator, and including a compound of a metal element M and a first group-IV semiconductor element Si 1−a−b  Ge a  C b,  where 0≦a≦1, 0≦b≦0.02, and 0≦a+b≦1,    the p-type semiconductor device including:    a p-channel region formed on a surface of the silicon substrate;    a p-type source region and a p-type drain region formed opposite to each other on a surface of the substrate interposing the p-channel region therebetween;    a second gate insulator formed on the surface of the p-channel region between the p-type source region and the p-type drain region; and    a second gate electrode formed on the second gate insulator, and including a compound of the metal element M and a second group-IV semiconductor element Si 1−c−d  Ge c  C d , where 0≦c≦1, 0≦d≦0.02, 0≦c+d≦1, a≠c and at least one of b and d≠0.    
   
   
       12 . The device according to  claim 11 , wherein the metal element M includes one selected from the group consisting of Ni, Pd, Pt, Ta, Er, Ti and Zr.  
   
   
       13 . The device according to  claim 11 , wherein the device satisfies conditions a≧0.3 and c≧0.3.  
   
   
       14 . The device according to  claim 11 , wherein the metal element M includes Ni, and satisfies a condition c>a.  
   
   
       15 . The device according to  claim 11 , wherein the metal element M includes two or more metal elements selected from the group consisting of Ni, Pd and Pt or includes Ti and Zr.  
   
   
       16 . The device according to  claim 11 , wherein at least one of the first gate electrode and the second gate electrode includes one selected from the group consisting of As, P and B.  
   
   
       17 . The device according to  claim 11 , wherein the p-type semiconductor device and the n-type semiconductor device are configured to be fully depleted.  
   
   
       18 . The device according to  claim 11 , wherein the p-type semiconductor device and the n-type semiconductor device form a complementary pair.  
   
   
       19 . The device according to  claim 11 , wherein the first gate electrode and the second gate electrode include B, and the first gate electrode satisfies a condition a≠0 while the second gate electrode satisfies a condition c=0, and b+d>0.  
   
   
       20 . The device according to  claim 1 , wherein Ge included in the first gate electrode is more than 5% with respect to Si.