MOS field effect transistor with reduced on-resistance

Abstract

A semiconductor substrate includes a first principal plane and a second principal plane opposite this first principal plane. A first semiconductor region is formed on the first principal plane of the semiconductor substrate. Second and third semiconductor regions are formed separately from each other on the first semiconductor region. A gate electrode is formed, via a gate insulator, on the first semiconductor region between the second semiconductor region and the third semiconductor region. An electric conductor is formed up to the semiconductor substrate from the second semiconductor region and electrically connects the second semiconductor region with the semiconductor substrate. A first main electrode is formed on the second principal plane of the semiconductor substrate and is electrically connected to the semiconductor substrate. A second main electrode is formed on the first semiconductor region via insulators and is electrically connected to the third semiconductor region.

1 - 21 . (canceled)  
   
   
       22 . A MOS field effect transistor comprising: 
 a semiconductor substrate of first conductive type;    a first semiconductor region of second conductive type formed on said semiconductor substrate;    a second semiconductor region of second conductive type formed between said semiconductor substrate and said first semiconductor region;    a third semiconductor region of first conductive type formed in said first semiconductor region;    a fourth semiconductor region of second conductive type formed in said third semiconductor region;    a fifth semiconductor region of second conductive type formed in said first semiconductor region separately from said fourth semiconductor region;    a gate electrode formed, via a gate insulator, on said first semiconductor region between said fourth semiconductor region and said fifth semiconductor region;    wherein said third semiconductor region and said second semiconductor region form a diode and a withstand voltage of this diode is set lower than a withstand voltage between said fourth semiconductor region and said fifth semiconductor region.    
   
   
       23 . The MOS field effect transistor according to  claim 22 , wherein said fifth semiconductor region includes a low-concentration region provided with a low impurity concentration and arranged near said gate electrode and a high-concentration region provided with a higher impurity concentration than that for said low-concentration region.  
   
   
       24 . The MOS field effect transistor according to  claim 23 , wherein said low-concentration region includes a first region arranged near said gate electrode and a second region arranged between this first region and said high-concentration region, and an impurity concentration for said second region is higher than that for said first region.  
   
   
       25 . The MOS field effect transistor according to  claim 22 , wherein said second semiconductor region is a buried layer.  
   
   
       26 . The MOS field effect transistor according to  claim 22 , wherein said fourth semiconductor region is a source region and said fifth semiconductor region is a drain region.  
   
   
       27 - 43 . (canceled)