Thin film transistor array panel

Abstract

The present invention provides a thin film transistor array panel comprising: an insulating substrate; a first signal line formed on the insulating substrate and extending in a first direction; a second signal line formed on the insulating substrate, extending in a second direction, and intersecting the first signal line; a thin film transistor connected to the first and second signal lines; a passivation layer formed on the second signal line and having a contact hole exposing a portion of the second signal line; and a pixel electrode formed on the passivation layer and connected to the thin film transistor through the contact hole, wherein the passivation layer is formed by coating an organic solution that includes an organic insulating material and a solvent including at least one of PGMEP, EEP, and nBA.

1 . A thin film transistor array panel comprising: 
 an insulating substrate;    a first signal line formed on the insulating substrate and extending in a first direction;    a second signal line formed on the insulating substrate, extending in a second direction, and intersecting the first signal line;    a thin film transistor connected to the first and second signal lines;    a passivation layer formed on the second signal line and having a contact hole exposing a portion of the second signal line; and    a pixel electrode formed on the passivation layer and connected to the thin film transistor through the contact hole,    wherein the passivation layer is formed by coating an organic solution that includes an organic insulating material and a solvent including at least one of PGMEP, EEP, and nBA.    
   
   
       2 . The thin film transistor array panel of  claim 1 , wherein the content ratio of PGMEP:EEP:nBA in the solvent is 50 to 90:30 to 5:20 to 5.  
   
   
       3 . The thin film transistor array panel of  claim 1 , wherein the organic solution further includes a surfactant comprising at least one of silane F and fluoric S.  
   
   
       4 . The thin film transistor array panel of  claim 3 , wherein the content ratio of silane F: fluoric S in the surfactant is 500 to 1500:50 to 500.  
   
   
       5 . A thin film transistor array panel comprising: 
 an insulating substrate;    a gate line formed on the insulating substrate;    a gate insulating layer formed on the gate line;    a semiconductor layer formed on the gate insulating layer;    a data line formed on the semiconductor layer;    a passivation layer formed on the data line and having a contact hole exposing a portion of the data line; and    a pixel electrode formed on the passivation layer and connected to the exposed portion of the data line through the contact hole,    wherein the passivation layer is formed by coating an organic solution that includes an organic insulating material and a solvent including at least one of PGMEP, EEP, and nBA.    
   
   
       6 . The thin film transistor array panel of  claim 5 , wherein the pixel electrode includes a transparent electrode and a reflection electrode having a transparent window.  
   
   
       7 . The thin film transistor array panel of  claim 6 , wherein the passivation layer has an embossed top surface.  
   
   
       8 . The thin film transistor array panel of  claim 5 , wherein the content ratio of PGMEP: EEP: nBA in the solvent is 50 to 90:30 to 5:20 to 5.  
   
   
       9 . The thin film transistor array panel of  claim 5 , wherein the organic solution further includes a surfactant comprising at least one of silane F and fluoric S.  
   
   
       10 . The thin film transistor array panel of  claim 9 , wherein the content ratio of silane F: fluoric S in the surfactant is 500 to 1500:50 to 500.  
   
   
       11 . A thin film transistor array panel comprising: 
 an insulating substrate;    a polysilicon layer formed on the insulating layer and including a source region, a drain region, and a channel region;    a gate insulating layer formed on the polysilicon layer;    a gate line formed on the gate insulating layer and including a gate electrode overlapping the channel region;    an interlayer insulating layer formed on the gate line;    a data line formed on the interlayer insulating layer and including a source electrode connected to the source region;    a drain electrode formed on the interlayer insulating layer and connected to the drain region;    an organic insulating layer formed on the drain electrode and the data line; and    a pixel electrode formed on the organic insulating layer and connected to the drain electrode,    wherein the organic insulating layer is formed by coating an organic solution that include an organic insulating material and a solvent including at least one of PGMEP, EEP, and nBA.    
   
   
       12 . The thin film transistor array panel of  claim 11 , wherein the pixel electrode includes a transparent electrode and a reflection electrode having a transparent window.  
   
   
       13 . The thin film transistor array panel of  claim 12 , wherein the organic insulating layer has an embossed top surface.  
   
   
       14 . The thin film transistor array panel of  claim 11 , wherein the content ratio of PGMEP:EEP:nBA in the solvent is 50 to 90:30 to 5:20 to 5.  
   
   
       15 . The thin film transistor array panel of  claim 11 , wherein the organic solution further includes a surfactant comprising at least one of silane F and fluoric S.  
   
   
       16 . The thin film transistor array panel of  claim 15 , wherein the content ratio of silane F: fluoric S in the surfactant is 500 to 1500:50 to 500.  
   
   
       17 . A thin film transistor array panel comprising: 
 an insulating substrate;    a polysilicon layer formed on the insulating layer and including source regions, drain regions, and channel regions;    a gate insulating layer formed on the polysilicon layer;    a plurality of gate lines formed on the gate insulating layer and including portions overlapping the channel regions;    a plurality of data line segments extending in a longitudinal direction and disposed between two adjacent gate lines;    an organic insulating layer formed on the gate lines and the data line segments and having contact holes;    a plurality of data connectors formed on the organic insulating layer, intersecting the gate lines, and connected to the data line segments through the contact holes; and    a plurality of pixel electrodes formed on the organic insulating layer and connected to the drain regions through the contact holes,    wherein the organic insulating layer is formed by coating an organic solution that includes an organic insulating material and a solvent including at least one of PGMEP, EEP, and nBA.    
   
   
       18 . The thin film transistor array panel of  claim 17 , wherein the pixel electrode includes a transparent electrode and a reflection electrode having a transparent window.  
   
   
       19 . The thin film transistor array panel of  claim 17 , wherein the organic insulating layer has an embossed top surface.  
   
   
       20 . The thin film transistor array panel of  claim 17 , wherein the content ratio of PGMEP: EEP: nBA in the solvent is 50 to 90:30 to 5:20 to 5.  
   
   
       21 . The thin film transistor array panel of  claim 17 , wherein the organic solution further includes a surfactant comprising at least one of silane F and fluoric S.  
   
   
       22 . The thin film transistor array panel of  claim 21 , wherein the content ratio of silane F:fluoric S in the surfactant is 500 to 1500:50 to 500.  
   
   
       23 . A thin film transistor array panel comprising: 
 an insulating substrate;    a gate line formed on the insulating;    a gate insulating layer formed on the gate line;    a semiconductor layer formed on the gate insulating layer;    a data line formed on the semiconductor layer;    a passivation layer formed on the data line and having a contact hole exposing a portion of the data line; and    a pixel electrode formed on the passivation layer and connected to the exposed portion of the data line through the contact hole,    wherein the pixel electrode includes a transparent electrode and a reflection electrode having a transparent window and the passivation layer includes 1% to 10% of a silane coupling agent (SCA) with respect to an amount of resin included in the passivation layer.    
   
   
       24 . The thin film transistor array panel of  claim 23 , wherein the passivation layer has an embossed top surface.  
   
   
       25 . The thin film transistor array panel of  claim 23 , wherein the SCA is represented by the structural formula of  
     
       
         
         
             
             
         
       
     
   
   
       26 . A thin film transistor array panel comprising: 
 an insulating substrate;    a gate line formed on the insulating substrate;    a gate insulating layer formed on the gate line;    a semiconductor layer formed on the gate insulating layer;    a data line formed on the semiconductor layer;    a passivation layer formed on the data line and having a contact hole exposing a portion of the data line; and    a pixel electrode formed on the passivation layer and connected to the exposed portion of the data line through the contact hole,    wherein the pixel electrode is a transparent electrode and the passivation layer includes 1% to 10% of a silane coupling agent (SCA) with respect to an amount of resin included in the passivation layer.    
   
   
       27 . The thin film transistor array panel of  claim 26 , wherein the SCA is represented by the structural formula of  
     
       
         
         
             
             
         
       
     
   
   
       28 . A thin film transistor array panel comprising: 
 an insulating substrate;    a polysilicon layer formed on the insulating layer and including a source region, a drain region, and a channel region;    a gate insulating layer formed on the polysilicon layer;    a gate line formed on the gate insulating layer and including a gate electrode overlapping the channel region;    an interlayer insulating layer formed on the gate line;    a data line formed on the interlayer insulating layer and including a source electrode connected to the source region;    a drain electrode formed on the interlayer insulating layer and connected to the drain region;    an organic insulating layer formed on the drain electrode and the data line; and    a pixel electrode formed on the organic insulating layer and connected to the drain electrode,    wherein the pixel electrode includes a transparent electrode and a reflection electrode having a transparent window and the organic insulating layer includes 1% to 10% of a silane coupling agent (SCA) with respect to an amount of resin included in the organic insulating layer.    
   
   
       29 . The thin film transistor array panel of  claim 28 , wherein the organic insulating layer has an embossed top surface.  
   
   
       30 . The thin film transistor array panel of  claim 28 , wherein the SCA is represented by the structural formula of  
     
       
         
         
             
             
         
       
     
   
   
       31 . A thin film transistor array panel comprising: 
 an insulating substrate;    a polysilicon layer formed on the insulating layer and including a source region, a drain region, and a channel region;    a gate insulating layer formed on the polysilicon layer;    a gate line formed on the gate insulating layer and including a gate electrode overlapping the channel region;    an interlayer insulating layer formed on the gate line;    a data line formed on the interlayer insulating layer and including a source electrode connected to the source region;    a drain electrode formed on the interlayer insulating layer and connected to the drain region;    an organic insulating layer formed on the drain electrode and the data line; and    a pixel electrode formed on the organic insulating layer and connected to the drain electrode,    wherein the pixel electrode is a transparent electrode and the organic insulating layer includes 1% to 30% of a silane coupling agent (SCA) with respect to an amount of resin included in the organic insulating layer.    
   
   
       32 . The thin film transistor array panel of  claim 31 , wherein the SCA is represented by the structural formula of  
     
       
         
         
             
             
         
       
     
   
   
       33 . A thin film transistor array panel comprising: 
 an insulating substrate;    a polysilicon layer formed on the insulating layer and including source regions, drain regions, and channel regions;    a gate insulating layer formed on the polysilicon layer;    a plurality of gate lines formed on the gate insulating layer and including portions overlapping the channel regions;    a plurality of data line segments extending in a longitudinal direction and disposed between two adjacent gate lines;    an organic insulating layer formed on the gate lines and the data line segments and having contact holes;    a plurality of data connectors formed on the organic insulating layer, intersecting the gate lines, and connected to the data line segments through the contact holes; and    a plurality of pixel electrodes formed on the organic insulating layer and connected to the drain regions through the contact holes,    wherein the organic insulating layer includes a transparent electrode and a reflection electrode having a transparent window and the organic insulating layer includes 1% to 10% of a silane coupling agent (SCA) with respect to an amount of resin included in the organic insulating layer.    
   
   
       34 . The thin film transistor array panel of  claim 33 , wherein the organic insulating layer has an embossed top surface.  
   
   
       35 . The thin film transistor array panel of  claim 33 , wherein the SCA is represented by the structural formula of  
     
       
         
         
             
             
         
       
     
   
   
       36 . A thin film transistor array panel comprising: 
 an insulating substrate;    a polysilicon layer formed on the insulating layer and including source regions, drain regions, and channel regions;    a gate insulating layer formed on the polysilicon layer;    a plurality of gate lines formed on the gate insulating layer and including portions overlapping the channel regions;    a plurality of data line segments extending in a longitudinal direction and disposed between two adjacent gate lines;    an organic insulating layer formed on the gate lines and the data line segments and having contact holes;    a plurality of data connectors formed on the organic insulating layer, intersecting the gate lines, and connected to the data line segments through the contact holes; and    a plurality of pixel electrodes formed on the organic insulating layer and connected to the drain regions through the contact holes,    wherein the organic insulating layer is a transparent electrode and the organic insulating layer includes 1% to 30% of a silane coupling agent (SCA) with respect to an amount of resin included in the organic insulating layer.    
   
   
       37 . The thin film transistor array panel of  claim 36 , wherein the polysilicon layer further comprises lightly doped drain regions formed between the source region and the channel region and between the drain region and the channel region.  
   
   
       38 . The thin film transistor array panel of  claim 36 , further comprising a blocking layer formed between the insulating layer and the polysilicon layer.  
   
   
       39 . The thin film transistor array panel of  claim 36 , wherein the SCA is represented by the structural formula of