Virtual first in first out direct memory access device

Abstract

A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO is provided. In the virtual FIFO DMA device, a DMA unit is for transferring data between the UART unit and the virtual FIFO. A virtual FIFO controller, which has a read pointer and a write pointer, is electrically connected with the DMA unit. When the DMA unit reads data from or saves data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer. A virtual port is electrically connected with the DMA unit and the processor respectively. A processor reads data from or writes data into the virtual FIFO via the virtual port and the DMA unit.

1 . A virtual first in first out (FIFO) direct memory access (DMA) device applied in an electronic device having a processor, a UART unit and a virtual FIFO, the virtual FIFO DMA device comprising: 
 a DMA unit, being respectively electrically connected with the UART unit and the virtual FIFO, for transferring data between the UART unit and the virtual FIFO;    a virtual FIFO controller, being electrically connected with the DMA unit, having a read pointer and a write pointer, wherein when the DMA unit reads data from or writes data into the virtual FIFO, the virtual FIFO controller correspondingly changes the value of read pointer or write pointer; and    a virtual port, being respectively electrically connected with the DMA unit and the processor, wherein the processor reads data from or writes date into the virtual FIFO through the virtual port and the DMA unit.    
   
   
       2 . The virtual FIFO DMA device according to  claim 1 , wherein the virtual FIFO controller has a read pointer and a write pointer for respectively pointing to a data reading location and a data writing location of the virtual FIFO, the UART unit has a data register, when the UART unit receives data up to a particular amount, the UART unit sends a request signal to request the DMA unit to transfer the data from the data register to the location where the write pointer WP points in the virtual FIFO, the DMA unit further sends a write notice signal to the virtual FIFO controller so that the virtual FIFO controller correspondingly changes the value of the write pointer; 
 wherein the virtual port has a peripheral device address and the processor takes the virtual FIFO DMA device as a peripheral device, when the processor reads the data in the virtual FIFO, the processor sends a reading signal to the virtual port and the virtual port sends a DMA read request to the DMA unit, the DMA unit reads the virtual FIFO to get a first data according to the read pointer, the DMA unit further sends a read notice signal to the virtual FIFO controller to change the value of the read pointer accordingly, the DMA unit transmits the first data to the virtual port, which in turn transmits the first data to the processor.    
   
   
       3 . The virtual FIFO DMA device according to  claim 1 , wherein the electronic device is a mobile phone.  
   
   
       4 . The virtual FIFO DMA device according to  claim 1 , wherein the virtual FIFO controller has a read pointer and a write pointer for respectively pointing to a data reading location and a data writing location of the virtual FIFO, the UART unit has a data register, when data of the processor need to be transmitted from the UART unit, the processor transmits a transmission instruction and a data-to-be-transmitted data to the virtual port, the virtual port sends a write request to the DMA unit, and the DMA unit writes the data-to-be-transmitted data to the virtual FIFO according to the value of the write pointer, the DMA unit sends a write notice signal to the virtual FIFO controller for the virtual FIFO controller to correspondingly change the value of the write pointer, the DMA unit sequentially transfers the data from the virtual FIFO to the data register of the UART unit.  
   
   
       5 . The virtual FIFO DMA device according to  claim 1 , wherein the virtual port has a peripheral device address and the processor takes the virtual FIFO DMA device as a peripheral device, when the processor reads data from the virtual port, the virtual port sends a DMA read request to the DMA unit, which in turn gets a first data from the virtual FIFO according to the read pointer, the virtual FIFO controller changes the value of the read pointer accordingly, the DMA unit transmits the first data to the virtual port, which in turn transmits the first data to the processor; 
 when the processor transmits a to-be-written second data to the virtual port, the virtual port sends a DMA write request to the DMA unit, which in turn writes the second data into the virtual FIFO according to the write pointer, the virtual FIFO controller changes the value of the write pointer.    
   
   
       6 . The virtual FIFO DMA device according to  claim 1 , wherein the virtual FIFO controller further has a flow control function, and the virtual FIFO controller disables all write instructions when the virtual FIFO is substantially full, and disables all read instructions when the virtual FIFO is substantially empty.  
   
   
       7 . An electronic device, comprising: 
 a virtual FIFO DMA device, comprising: 
 a DMA unit;  
 a virtual port, being electrically connected with DMA unit; and  
 a virtual FIFO controller, being electrically connected with the DMA unit, having a read pointer and a write pointer;  
   a UART unit, being electrically connected with the DMA unit;    a virtual FIFO, being electrically connected with the DMA unit, wherein the DMA unit transfers data between the UART unit and the virtual FIFO, and the virtual FIFO controller correspondingly changes the value of the read pointer or the write pointer when the DMA unit reads data from or writes data into the virtual FIFO; and    a processor, being electrically connected with virtual port, wherein the processor reads data from or writes data into the virtual FIFO through the virtual port and the DMA unit.    
   
   
       8 . An electronic device according to  claim 7 , wherein the UART unit has a data register, and data of the data register is transferred to the virtual FIFO by the DMA unit when the data register is full.  
   
   
       9 . The virtual FIFO DMA device according to  claim 8 , wherein the electronic device is a mobile phone.  
   
   
       10 . The virtual FIFO DMA device according to  claim 7 , wherein the virtual port has a peripheral device address, and the processor takes the virtual FIFO DMA device as a peripheral device, when the processor reads data from the virtual port, the virtual port sends a DMA read request to the DMA unit, which in turn reads a first data from the virtual FIFO according to the read pointer, the virtual FIFO controller changes the value of the read pointer accordingly, the DMA unit transmits the first data to the virtual port, which in turn transmits the first data to the processor; 
 when the processor transmits a to-be-written second data to the virtual port, the virtual port sends a DMA write request to the DMA unit, which in turn writes the second data into the virtual FIFO according to the write pointer, the virtual FIFO controller changes the value of the write pointer.    
   
   
       11 . The virtual FIFO DMA device according to  claim 7 , wherein the virtual FIFO controller further has a flow control function, and the virtual FIFO controller disables all write instructions when the virtual FIFO is substantially full and disables all read instructions when the virtual FIFO is substantially empty.  
   
   
       12 . A virtual first in first out (FIFO) direct memory access (DMA) method applied in a virtual FIFO DMA device of an electronic device, the electronic device having a processor, a UART unit and a virtual FIFO, the FIFO DMA device having a DMA unit, a virtual FIFO controller, and a virtual port, the virtual FIFO controller having a read pointer and a write pointer, the UART unit having a data register, the virtual port having a peripheral device address, and the processor taking the virtual FIFO DMA device as a peripheral device, the virtual FIFO DMA method comprising: 
 when the UART unit receives data up to a particular amount, the UART unit sending a request signal to request the DMA unit to transfer the data from the data register to the location where the write pointer WP points in the virtual FIFO, the DMA unit further sending a write notice signal to the virtual FIFO controller so that the virtual FIFO controller correspondingly changes the value of the write pointer;    when the processor reads the data in the virtual FIFO, the processor sending a reading signal to the virtual port and the virtual port sending a DMA read request to the DMA unit, the DMA unit reading the virtual FIFO to get a first data according to the read pointer, the DMA unit further sending a read notice signal to the virtual FIFO controller so that the virtual FIFO controller changes the value of the read pointer accordingly, the DMA unit transmitting the first data to the virtual port, which in turn transmits the first data to the processor;    when data of the processor need to be transmitted by the UART unit, the processor transmitting a transmission instruction and a data-to-be-transmitted data to the virtual port, the virtual port sending a write request to the DMA unit and the DMA unit writing the data-to-be-transmitted data to the virtual FIFO according to the value of the write pointer, the DMA unit sending a write notice signal to the virtual FIFO controller for the virtual FIFO controller to correspondingly change the value of the write pointer, the DMA unit sequentially transferring the data from the virtual FIFO to the data register of the UART unit.    
   
   
       13 . The virtual FIFO DMA device according to  claim 12 , wherein the electronic device is a mobile phone.