Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors

Abstract

A method for forming a transistor includes forming a gate dielectric layer over a portion of a semiconductor substrate, the substrate being substantially free of silicon; defining a gate electrode over a portion of the gate dielectric layer; and introducing ions into the substrate proximate the gate electrode to define source and drain regions. A transistor includes a semiconductor substrate that is substantially free of silicon and a gate, dielectric layer over a portion of the substrate. The transistor can also include a gate electrode over a portion of the gate dielectric layer and introduce ions proximate the gate electrode, defining source and drain regions.

1 . A method for forming a transistor, comprising: 
 forming a gate dielectric layer over a portion of a semiconductor substrate, the substrate being substantially free of silicon;    defining a gate electrode over a portion of the gate dielectric layer; and    introducing ions into the substrate proximate the gate electrode to define a source region and a drain region.    
   
   
       2 . The method of  claim 1 , further comprising: 
 depositing an interlayer dielectric layer over at least part of the gate electrode, the source region, and the drain region;    defining first, second, and third openings in the interlayer dielectric layer over at least part of the gate electrode, the source region, and the drain region; and    depositing a metal into the first, second, and third openings to contact the gate electrode, the source region, and the drain region.    
   
   
       3 . The method of  claim 1 , wherein the substrate comprises a material having a carrier mobility greater than a carrier mobility of silicon.  
   
   
       4 . The method of  claim 3 , wherein the substrate comprises at least one of germanium, indium antimonide, indium phosphide, gallium arsenide, indium arsenide, and lead telluride.  
   
   
       5 . The method of  claim 1 , wherein the gate dielectric comprises a material having a high dielectric constant, the high dielectric constant being at least twice a dielectric constant of silicon dioxide.  
   
   
       6 . The method of  claim 5 , wherein the gate dielectric comprises at least one of aluminum oxide, hafnium oxide, zirconium silicon oxide, strontium titanium oxide, tantalum oxide, barium titanium oxide, zirconium oxide, yttrium oxide, barium strontium titanium oxide, and silicon nitride.  
   
   
       7 . The method of  claim 1 , wherein the gate electrode comprises at least one of titanium nitride, tantalum nitride, titanium, tantalum, nickel, platinum, polygermanium, and polysilicon.  
   
   
       8 - 21 . (canceled)  
   
   
       22 . The method of  claim 1 , wherein the gate the gate dielectric layer comprises a metal oxide having a dielectric constant greater than 7.8.  
   
   
       23 . The method of  claim 1 , wherein the gate the gate dielectric layer has a thickness that is large enough to reduce gate leakage current.  
   
   
       24 . The method of  claim 1 , wherein the gate the gate dielectric layer comprises a compound having a free energy of formation that is lower than a free energy of formation of a compound that is formed between the material and the semiconductor substrate  
   
   
       25 . The method of  claim 1 , wherein defining the gate electrode includes defining the gate electrode such that the gate dielectric layer has a cross-sectional area substantially similar to a cross-sectional area of the gate electrode.  
   
   
       26 . The method of  claim 1 , wherein the semiconductor substrate has a bandgap narrower than a bandgap of silicon.