Flash memory cell and method of manufacturing the same and programming/erasing/reading method of flash memory cell

Abstract

Disclosed is a flash memory cell and method of manufacturing the same, and programming/erasing/reading method thereof. The flash memory cell comprises a first tunnel oxide film formed at a given region of a semiconductor substrate, a first floating gate formed on the first tunnel oxide film, a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate, a second floating g ate isolated from the first floating gate while contacting the second tunnel oxide film, a dielectric film formed on the first floating gate and the second floating gate, a control gate formed on the dielectric film, a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film, and a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film. Therefore, the present invention can implement 2-bit cell or 3-bit cell of a high density using the existing process technology. Further, it can reduce the manufacture cost and implement a high-integrated flash memory cell that is advantageous than a conventional flash memory cell in view of charge storage/retention as well as programming time.

1 . A flash memory cell, comprising: 
 a first tunnel oxide film formed at a given region of a semiconductor substrate;    a first floating gate formed on the first tunnel oxide film;    a second tunnel oxide film formed over the semiconductor substrate and along one sidewall of the first floating gate;    a second floating gate isolated from the first floating gate while contacting the second tunnel oxide film;    a dielectric film formed on the first floating gate and the second floating gate;    a control gate formed on the dielectric film;    a first junction region formed in the semiconductor substrate below one side of the second tunnel oxide film; and    a second junction region formed in the semiconductor substrate below one side of the first tunnel oxide film.    
   
   
       2 . The flash memory cell as claimed in  claim 1 , wherein data of 2-bit is stored at 1 (one) cell, by injecting electrons into the first floating gate and the second floating gate and discharging electrons injected into the first floating gate and the second floating gate depending on a voltage applied to the control gate, the first junction region and the second junction region.  
   
   
       3 . The flash memory cell as claimed in  claim 1 , wherein data of 3-bit is stored at 1(one) cell by storing data of 1 bit at the second floating gate and storing data of 2-bit at the first floating gate, by injecting electrons into the first floating gate and the second floating gate and discharging electrons injected into the first floating gate and the second floating gate, depending on a voltage applied to the control gate, the first junction region and the second junction region.  
   
   
       4 . The flash memory cell as claimed in  claim 1 , wherein the second tunnel oxide film is formed using a high-temperature oxide film.  
   
   
       5 . The flash memory cell as claimed in  claim 1 , wherein the second tunnel oxide film has a thickness of 50˜100 Å.  
   
   
       6 . The flash memory cell as claimed in  claim 1 , wherein the first floating gate is formed using a polysilicon film and the second floating gate is formed using a silicon nitride film.  
   
   
       7 . The flash memory cell as claimed in  claim 1 , wherein the first floating gate has a thickness of 500˜2000 Å.  
   
   
       8 . The flash memory cell as claimed in  claim 1 , wherein the second floating gate has a thickness of 100˜1000 Å.  
   
   
       9 . A programming method of a flash memory cell for storing data at the flash memory cell claimed in  claim 1 , being characterized in that: 
 if electrons are to be injected into the first floating gate, a programming operation is performed by applying a programming voltage to the control gate, connecting the first junction region and the ground terminal and applying a voltage lower than the programming voltage but higher than the ground voltage to the second junction region, and    if the electrons are to be injected into the second floating gate, the programming operation is performed by applying a programming voltage to the control gate, applying a voltage lower than the programming voltage but higher than the ground voltage to the first junction region and connecting the second junction region and the ground terminal,    wherein the programming operations are independently performed for the first floating gate and the second floating gate.    
   
   
       10 . The programming method as claimed in  claim 9 , wherein the programming voltage is 7V˜9V, and the voltage lower than the programming voltage but higher than the ground voltage is 4V˜5V.  
   
   
       11 . An erasing method of a flash memory cell for erasing data stored at the flash memory cell claimed in  claim 1 , being characterized in that: 
 if electrons injected into the first floating gate are to be discharged, an erasing operation is performed by applying an erasing voltage to the control gate, and applying a voltage higher than the ground voltage to the second junction region with the first junction region floated, and    if electrons injected into the second floating gate are to be discharged, the erasing operation is performed by applying the erasing voltage to the control gate, and applying a voltage higher than the ground voltage to the first junction region with the second junction region floated,    wherein the erasing operations are independently performed for the first floating gate and the second floating gate.    
   
   
       12 . The erasing method as claimed in  claim 11 , wherein the erasing voltage is −8V˜−9V, and the voltage higher than the ground voltage is 4V˜5V.  
   
   
       13 . An erasing method of a flash memory cell for erasing data stored at the flash memory cell claimed in  claim 1 , being characterized in that: 
 an erasing operation is performed by simultaneously discharging electrons injected into the first floating gate and the second floating gate, by applying an erasing voltage to the control gate and a voltage higher than the ground voltage to the semiconductor substrate, with the first junction region and the second junction region floated.    
   
   
       14 . The erasing method as claimed in  claim 13 , wherein the erasing voltage is −8V˜−9V, and the voltage higher than the ground voltage is 8V˜9V.  
   
   
       15 . A reading method of a flash memory cell for reading data stored at the flash memory cell claimed in  claim 1 , being characterized in that: 
 a reading operation is performed by applying a reading voltage to the control gate, connecting the first junction region to the ground terminal, applying a voltage lower than the reading voltage but higher than the ground voltage to the second junction region and then sensing cell current flowing into the second junction region, or by applying the reading voltage to the control gate, connecting the second junction region to the ground terminal, applying a voltage lower than the reading voltage but higher the ground voltage to the first junction region, and then sensing cell current flowing into the first junction region.    
   
   
       16 . The reading method as claimed in  claim 14 , wherein the reading voltage is 4V˜5V, and the voltage lower than the reading voltage but higher than the ground voltage is 0.8V˜1V.