Semiconductor nano-rod devices

Abstract

In a method of manufacturing a semiconductor device, a semiconductor layer is patterned to form a source region, a channel region, and a drain region in the semiconductor layer. The channel region extends between the source region and the drain region. Corners of the channel region are rounded by annealing the channel region to form a nano-rod structure. Part of the nano-rod structure is then used as a gate channel. Preferably, a gate dielectric and a gate electrode both wrap around the nano-rod structure, with the gate dielectric being between the nano-rod structure and the gate electrode, to form a transistor device.

1 . A semiconductor device comprising: 
 an insulating layer over an underlying layer;    a layer of semiconductor material over the insulating layer, the semiconductor layer having a source region, a drain region, and an annealed nano-rod structure extending between the source and drain regions;    a gate dielectric formed on the surface of at least a segment of the nano-rod structure; and    a gate electrode formed on the surface of the gate dielectric at the segment.    
     
     
         2 . The semiconductor device of  claim 1 , wherein the gate dielectric is formed completely around the nano-rod structure at the segment.  
     
     
         3 . The semiconductor device of  claim 2 , wherein the gate electrode is formed completely around the nano-rod structure at the segment.  
     
     
         4 . The semiconductor device of  claim 1 , wherein the semiconductor material is selected from a group consisting of silicon, germanium, silicon-germanium alloy, silicon-germanium-carbon alloy, indium phosphide compound, and gallium arsenide compound.  
     
     
         5 . The semiconductor device of  claim 1 , wherein the insulating layer comprises a material selected from a group consisting of silicon dioxide, silicon nitride, and aluminum oxide.  
     
     
         6 . The semiconductor device of  claim 1 , wherein the underlying layer is a silicon substrate.  
     
     
         7 . The semiconductor device of  claim 1 , wherein the gate dielectric comprises a material selected from a group consisting of silicon dioxide, silicon oxynitride, HfO2, ZrO2, Al2O3, and La2O3.  
     
     
         8 . The semiconductor device of  claim 1 , wherein the gate electrode comprises a material selected from a group consisting of a semiconducting material, a metal, and a metal nitride.  
     
     
         9 . The semiconductor device of  claim 1 , wherein the nano-rod structure has a cross-section diameter less than about 65 nm.  
     
     
         10 . The semiconductor device of  claim 1 , wherein the nano-rod structure has a substantially circular cross-section.  
     
     
         11 . The semiconductor device of  claim 1 , wherein the nano-rod structure has rounded corners.  
     
     
         12 . A semiconductor device comprising a plurality of transistors, wherein each of the plurality of transistors comprises: 
 an annealed semiconductor layer having a source region, a drain region, and a channel region formed therein, the channel region extending between the source region and the drain region, the channel region comprising a nano-rod structure with rounded corners;    a gate dielectric formed on the surface of at least a segment of the nano-rod structure; and    a gate electrode formed on the surface of the gate dielectric at the segment, the gate electrode having a gate contact region extending therefrom.    
     
     
         13 . The semiconductor device of  claim 12 , wherein the gate dielectric is formed completely around the nano-rod structure at the segment.  
     
     
         14 . The semiconductor device of  claim 13 , wherein the gate electrode is formed completely around the nano-rod structure at the segment.  
     
     
         15 . The semiconductor device of  claim 12 , wherein the semiconductor material is selected from a group consisting of silicon, germanium, silicon-germanium alloy, silicon-germanium-carbon alloy, indium phosphide compound, and gallium arsenide compound.  
     
     
         16 . The semiconductor device of  claim 12 , further comprising an insulating layer over an underlying layer, wherein the semiconductor layer is formed over the insulating layer.  
     
     
         17 . The semiconductor device of  claim 16 , wherein the insulating layer comprises a material selected from a group consisting of silicon dioxide, silicon nitride, and aluminum oxide, and wherein the underlying layer is a silicon substrate.  
     
     
         18 . The semiconductor device of  claim 12 , wherein the gate dielectric comprises a material selected from a group consisting of silicon dioxide, silicon oxynitride, HfO2, ZrO2, Al2O3, and La2O3, and wherein the gate electrode comprises a material selected from a group consisting of a semiconducting material, a metal, and a metal nitride.  
     
     
         19 . The semiconductor device of  claim 12 , wherein the nano-rod structure has a cross-section diameter less than about 65 nm.  
     
     
         20 . A semiconductor device comprising a plurality of transistors, wherein each of the plurality of transistors comprises: 
 an annealed semiconductor layer having a source region, a drain region, and a channel region formed therein, the channel region extending between the source region and the drain region, the channel region having a substantially circular cross-section shape,    a gate dielectric layer around a segment of the channel region, and    a gate electrode having a gate wrap region that wraps around the segment of the channel region and a gate contact region extending therefrom, wherein the gate dielectric layer is between the segment of the channel region and the gate wrap region of the gate electrode.