Clock generation systems and methods

Abstract

A low power reconfigurable processor core includes one or more processing units, each unit having a clock input that controls the performance of the unit; a wireless transceiver transmitting and receiving at a frequency based on a wireless clock input; and a controller having a plurality of clock outputs each coupled to the clock inputs of the processing units and the wireless clock input, the clock outputs being generated from a common master clock.

1 - 20 . (canceled)  
     
     
         21 : An integrated circuit, comprising: 
 a plurality of processor units, each having a clock input to clock the unit;    a wireless transceiver to transmit and receive at a frequency based on a wireless clock input; and    a controller having a plurality of clock outputs each coupled to a respective clock input of one of the processor units, the controller to control a frequency of the clock input of each processor unit and the wireless clock input, the plurality of clock outputs generated from a common master clock.    
     
     
         22 : The integrated circuit of  claim 21 , wherein the common master clock to operate at the same frequency as a Bluetooth frequency or an 802.11 frequency.  
     
     
         23 : The integrated circuit of  claim 21 , wherein at least one of the plurality of processor units comprises a digital signal processor (DSP) or a reduced instruction set computer (RISC) processor.  
     
     
         24 : The integrated circuit of  claim 21 , wherein the controller to independently rate control the plurality of clock outputs.  
     
     
         25 : The integrated circuit of  claim 21 , wherein the controller to change the clock input of at least one of the plurality of processor units independently of the remaining processor units.  
     
     
         26 : The integrated circuit of  claim 21 , further comprising an antenna comprising at least one clock trace coupled to the controller.  
     
     
         27 : The integrated circuit of  claim 21 , wherein the controller to vary a clock signal period of at least one of the plurality of clock outputs.  
     
     
         28 : The integrated circuit of  claim 21 , wherein the controller to phase modulate at least one of the plurality of clock outputs.  
     
     
         29 : A system comprising: 
 a first processor;    a wireless circuit coupled to the first processor, the wireless circuit comprising: 
 a second processor having a clock input to clock the second processor; and  
 a wireless transceiver to transmit and receive at a frequency based on a wireless clock input; and  
   a single clock generator to generate the clock input for the second processor and the wireless clock input for the wireless transceiver.    
     
     
         30 : The system of  claim 29 , wherein the wireless transceiver comprises a cellular radio core.  
     
     
         31 : The system of  claim 30 , wherein the wireless transceiver comprises a short-range radio core.  
     
     
         32 : The system of  claim 29 , wherein the second processor comprises a plurality of processor units, each coupled to receive an independent clock input from the single clock generator.  
     
     
         33 : The system of  claim 29 , wherein the wireless circuit comprises a single substrate.  
     
     
         34 : The system of  claim 29 , further comprising an input device coupled to the first processor to receive visual information.  
     
     
         35 : A method comprising: 
 generating a plurality of clock signals from a common master clock;    providing a first one of the plurality of clock signals to a wireless transceiver;    providing others of the plurality of clock signals to respective ones of a plurality of processor units; and    operating the respective plurality of processor units with the clock signals.    
     
     
         36 : The method of  claim 35 , further comprising independently controlling a frequency of the plurality of clock signals coupled to the respective plurality of processor units.  
     
     
         37 : The method of  claim 35 , further comprising clocking the wireless transceiver and the plurality of processor units at different frequencies.  
     
     
         38 : The method of  claim 35 , further comprising varying a clock signal period of the plurality of clock signals.  
     
     
         39 : The method of  claim 35 , wherein the wireless transceiver and the plurality of processor units are on a single substrate.