US2005116304A1PendingUtilityA1

Semiconductor device and manufacturing method thereof

Priority: Sep 17, 2002Filed: Jan 10, 2005Published: Jun 2, 2005
Est. expirySep 17, 2022(expired)· nominal 20-yr term from priority
H10W 10/17H10W 10/014H10W 10/01H10W 10/00H10D 84/0151H10D 84/0144H10D 84/038
45
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

In a semiconductor device including a plurality of element regions and an element isolation region based on STI (shallow trench isolation) which electrically isolates the element regions from each other, each of the element regions includes; a channel region; source/drain regions formed to sandwich the channel region in a horizontal direction; a gate insulation film which is formed on the channel region and in which an angle of a bird's beak is 1 degree or smaller, the bird's beak being formed from a side of the element isolation region on a surface opposite a surface facing the channel region in a horizontal direction substantially perpendicular to the direction in which the source/drain region sandwich the channel region; and a gate electrode layer formed on the gate insulation film.

Claims

exact text as granted — not AI-modified
1 - 9 . (canceled)  
   
   
       10 . A semiconductor device manufacturing method, comprising: 
 forming a gate insulation film on a substrate;    forming a gate electrode layer on the gate insulation film;    forming a trench structured to pass through the gate electrode layer and the gate insulation film and to dig into the substrate; and    burying an insulation film in the trench to be in direct contact with a side surface of the gate electrode layer in the trench and a side surface of the substrate in the trench.    
   
   
       11 . A semiconductor device manufacturing method as set forth in  claim 10 , wherein, in the forming the gate electrode layer on the gate insulation film, a polycrystalline silicon layer is formed as the gate electrode layer.  
   
   
       12 . A semiconductor device manufacturing method as set forth in  claim 10 , wherein, in the forming the trench structured to pass through the gate electrode layer and the gate insulation film and to dig into the substrate, a plurality of trenches substantially parallel to each other are formed, and the trenches are formed to make an internal dimension between the trenches parallel and adjacent to each other be 200 nm or smaller.

Join the waitlist — get patent alerts

Track US2005116304A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.