Interruption control system and method

Abstract

An interruption control system includes a first input/output interruption controller, a second input/output interruption controller and an interruption status indicating path. The first input/output interruption controller is coupled to a first peripheral device and a south bridge chip, and issues a wake-up signal to the south bridge chip in response to a first interrupt signal asserted by the first peripheral device so as to deactivate a power-saving state of the computer system. The second input/output interruption controller is coupled to a second peripheral device and a north bridge chip, and in response to a second interrupt signal asserted by the second peripheral device, generates a message signaled interrupt. The interruption status indicating path transmits the message signaled interrupt from the second input/output interruption controller to the south bridge chip to have the south bridge chip deactivate the power-saving state of the computer system in response to the message signaled interrupt.

1 . An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device and a second peripheral device, said interrupt control system comprising: 
 a first input/output interruption controller coupled to said first peripheral device and said south bridge chip, and issuing a wake-up signal to said south bridge chip in response to a first interrupt signal asserted by said first peripheral device so as to deactivate a power-saving state of said computer system;    a second input/output interruption controller coupled to said second peripheral device and said north bridge chip, and in response to a second interrupt signal asserted by said second peripheral device, generating a message signaled interrupt; and    an interruption status indicating path for transmitting said message signaled interrupt from said second input/output interruption controller to said south bridge chip to have said south bridge chip deactivate said power-saving state of said computer system in response to said message signaled interrupt.    
   
   
       2 . The interruption control system according to  claim 1  further comprising a stop clock control module coupled to said first input/output interruption controller and said CPU, optionally asserting a stop clock signal to have said CPU enter a power-saving state and de-asserting said stop clock signal to have said CPU deactivate said power-saving state in response to said wake-up signal from said first input/output interruption controller or said message signaled interrupt from said second input/output interruption controller.  
   
   
       3 . The interruption control system according to  claim 2  wherein said interruption status indicating path is an interruption status indicating pin electrically connected between said second input/output interruption controller and said stop clock control module of said south bridge chip for transmitting said message signaled interrupt from said second input/output interruption controller to said stop clock control module.  
   
   
       4 . The interruption control system according to  claim 2  wherein said first input/output interruption controller and said stop clock control module are integrated into said south bridge chip.  
   
   
       5 . The interrupt control system according to  claim 1  wherein said first input/output interruption controller is an input/output advanced programmable interrupt controller.  
   
   
       6 . The interruption control system according to  claim 1  wherein said second input/output interruption controller is an input/output advanced programmable interrupt controller disposed in a bus bridge chip between said north bridge chip and said second peripheral device.  
   
   
       7 . The interruption control system according to  claim 6  wherein said interruption status indicating path includes a first data bus between said bus bridge chip and said north bridge chip and a second data bus between said north bridge chip and said south bridge chip for transmitting said message signaled interrupt from said second input/output interruption controller to a stop clock control module of said south bridge chip, which optionally asserts a stop clock signal to have said CPU enter a power-saving state and asserts a stop clock signal to have said CPU deactivate said power-saving state in response to said wake-up signal from said first input/output interruption controller or said message signaled interrupt from said second input/output interruption controller.  
   
   
       8 . The interrupt control system according to  claim 6  wherein said bus bridge chip is a PCI-to-PCI bridge chip.  
   
   
       9 . The interrupt control system according to  claim 1  wherein said message signaled interrupt is an interrupt message of a memory write cycle.  
   
   
       10 . An interruption control system for use with a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip, and a peripheral device coupled to said north bridge chip, said interrupt control system comprising: an input/output interruption controller coupled to said second peripheral device and said north bridge chip and asserting a message signaled interrupt in response to an interrupt signal asserted by said second peripheral device; and a stop clock control module coupled to said CPU via a stop clock signal pin and to said input/output interruption controller via an interrupt status indicating pin, and de-asserting a stop clock signal previously asserted to said CPU via said stop clock signal pin to deactivate a power-saving state of said computer system in response to said message signaled interrupt received via said interrupt status indicating pin.  
   
   
       11 . The interruption control system according to  claim 10  further comprising another input/output interruption controller coupled to said stop clock control module for alternatively triggering said stop clock control module to de-assert said stop clock signal in response to an interrupt signal issued by said first peripheral device, said another input/output interruption controller being integrated into said south bridge chip together with said stop clock control module.  
   
   
       12 . The interruption control system according to  claim 11  wherein said input/output controllers are both input/output advanced programmable interrupt controllers.  
   
   
       13 . The interruption control system according to  claim 10  wherein said input/output interruption controller is disposed in a PCI-to-PCI bridge chip.  
   
   
       14 . The interrupt control system according to  claim 10  wherein said message signaled interrupt is an interrupt message of a memory write cycle.  
   
   
       15 . An interruption control method of a computer system, said computer system comprising a CPU, a north bridge chip, a south bridge chip, a first peripheral device coupled to said south bridge chip and a second peripheral device coupled to said north bridge chip via a bus bridge chip, said method comprising steps of: 
 issuing a message signaled interrupt in response to an interrupt signal from said second peripheral device and transmitting said message signaled interrupt to said south bridge chip via a first data bus between said bus bridge chip and said north bridge chip and a second bus between said north bridge chip and said south bridge chip; and    de-asserting a stop clock signal that is previously asserted by said south bridge chip to deactivate a power-saving state of said computer system in response to said message signaled interrupt.    
   
   
       16 . The method according to  claim 15  further comprising steps of: 
 issuing a wake-up signal in response to another interrupt signal from said first peripheral device; and    de-asserting said stop clock signal in response to said wake-up signal.    
   
   
       17 . The method according to  claim 16  wherein said wake-up signal is issued by an input/output advanced programmable interrupt controller disposed in said south bridge chip.  
   
   
       18 . The method according to  claim 15  wherein said message signaled interrupt is issued by an input/output advanced programmable interrupt controller disposed in said bus bridge chip.  
   
   
       19 . The method according to  claim 15  wherein said message signaled interrupt is an interrupt message of a memory write cycle.