Semiconductor device with multi-bank DRAM and cache memory

Abstract

To provide means that can hide refresh operations even when the data width of a cache line differs from that of the external data bus in a memory that uses a cache memory and a DRAM consisting of a plurality of banks. A semiconductor device consisting of a plurality of memory banks BANK 0 to BANK 127, each consisting of a plurality of memory cells, as well as a cache memory CACHEMEM used to retain information read from the plurality of memory banks. The cache memory CACHEMEM consists of a plurality of entries, each having a data memory DATAMEM and a tag memory TAGMEM. The data memory DATAMEM consists of a plurality of sub lines DATA 0 to DATA 3 and the tag memory TAGMEM Consists of a plurality of valid bits V 0 to V 3 and a plurality of dirty bits D 0 to D 3. It is possible to realize a memory with excellent operability, causing no refresh operation to delay external accesses. In other words, it is possible to realize a memory compatible with an SRAM in which refresh operations are hidden from external.

1 - 20 . (canceled)  
   
   
       21 . A semiconductor device comprising: 
 a memory array including a plurality of memory banks, each of the plurality of memory banks including a plurality of memory cells;    a cache memory coupled to the plurality of memory banks via an internal data bus; and    a plurality of data input/output nodes coupled to an external bus, the plurality of data input/output nodes being used to output information stored in the memory array to outside of the semiconductor device,    wherein the cache memory has a plurality of entries,    wherein each of the plurality of entries has a data part that stores information read from some of the plurality of memory banks, and a tag part that stores address information corresponding to the information stored in the data part,    wherein the data part has a plurality of sub lines, and    wherein A=N•B is satisfied where the number of the sub lines is N, the data width of the internal data bus is A, and the data width of the external data bus is B.    
   
   
       22 . A semiconductor device according to  claim 21 , 
 wherein a data width of information in each of the plurality of sub lines is identical to the data width of the external data bus.    
   
   
       23 . A semiconductor device according to  claim 21 , 
 wherein each of said plurality of memory cells is a two-transistor memory cell.    
   
   
       24 . A semiconductor device according to  claim 21 , 
 wherein each of said plurality of memory cells is a three-transistor memory cell.    
   
   
       25 . A semiconductor device according to  claim 21 , 
 wherein data is transferred from the memory array to the cache memory via a first port internal data bus, and data is transferred from the cache memory to the memory array via a second port internal data bus.    
   
   
       26 . A semiconductor device according to  claim 25 , 
 wherein a data width of the first port internal data bus is A, and a data width of the second port internal data bus is A.