US2005110114A1PendingUtilityA1
Capacitor formed on a recrystallized polysilicon layer and a method of manufacture therefor
Est. expiryNov 25, 2023(expired)· nominal 20-yr term from priority
H10D 1/68H10B 12/03
38
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Claims
Abstract
The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device, among other elements, includes a recrystallized polysilicon layer 148 located over a gate electrode layer 143 , a capacitor 170 located on the recrystallized polysilicon layer 148 . The capacitor 170 , in this embodiment, includes a first electrode 173 , an insulator 175 located over the first electrode 173 , and a second electrode 178 located over the insulator 175.
Claims
exact text as granted — not AI-modified1 . (canceled)
2 . A semiconductor device, comprising:
a recrystallized polysilicon layer located over a gate electrode layer; and a capacitor located on said recrystallized polysilicon layer, said capacitor, including;
a first electrode;
an insulator located over said first electrode; and
a second electrode located over said insulator.
wherein said first electrode comprises a silicide.
3 . The semiconductor device as recited in claim 2 wherein said first electrode comprises cobalt silicide.
4 . The semiconductor device as recited in claim 2 wherein said first electrode has a surface roughness ranging from about 1 nm to about 2 nm.
5 . A semiconductor device, comprising:
a recrystallized polysilicon layer located over a gate electrode layer; and a capacitor located on said recrystallized polysilicon layer, said capacitor, including;
a first electrode;
an insulator located over said first electrode; and
a second electrode located over said insulator;
wherein at least a portion of said recrystallized polysilicon layer forms a portion of said first electrode.
6 . The semiconductor device as recited in claim 5 wherein said recrystallized polysilicon layer has a final thickness ranging from about 7 nm to about 35 nm.
7 . A semiconductor device, comprising:
a recrystallized polysilicon layer located over a gate electrode layer; and a capacitor located on said recrystallized polysilicon layer, said capacitor, including;
a first electrode;
an insulator located over said first electrode; and
a second electrode located over said insulator;
wherein said gate electrode layer is a polysilicon layer and said recrystallized polysilicon layer is located on said polysilicon layer.
8 . The semiconductor device as recited in claim 7 wherein said polysilicon layer and said recrystallized polysilicon layer form at least a portion of a gate electrode stack.
9 . A method for manufacturing a semiconductor device, comprising:
forming an amorphous silicon layer over a substrate; changing said amorphous silicon layer to a recrystallized polysilicon layer; and creating a capacitor on said recrystallized polysilicon layer, said capacitor including;
a first electrode;
an insulator located over said first electrode;
a second electrode located over said insulator.
10 . The method as recited in claim 9 wherein forming an amorphous silicon layer includes depositing an amorphous silicon layer having a thickness ranging from about 15 nm to about 75 nm.
11 . The method as recited in claim 9 wherein changing said amorphous silicon layer to a recrystallized polysilicon layer includes subjecting said amorphous silicon layer to an annealing process, said annealing process causing said amorphous silicon layer to become said recrystallized polysilicon layer.
12 . The method as recited in claim 11 wherein subjecting said amorphous silicon layer to an annealing process includes subjecting said amorphous silicon layer to a temperature ranging from about 1000□ C to about 1100□ C.
13 . The method as recited in claim 9 wherein forming an amorphous silicon layer over a substrate includes forming an amorphous silicon layer on a polysilicon layer, wherein said amorphous silicon layer and said polysilicon layer form at least a part of a gate electrode stack.
14 . The method as recited in claim 13 wherein said amorphous silicon layer has a thickness ranging from about 15 nm to about 75 nm and said polysilicon layer has a thickness ranging from about 50 nm to about 150 nm.
15 . The method as recited in claim 9 wherein creating a capacitor first electrode includes creating a capacitor first electrode comprising a silicide.
16 . The method as recited in claim 14 wherein said silicide comprises cobalt silicide.
17 . The method as recited in claim 9 wherein creating a capacitor first electrode includes creating a capacitor first electrode having a surface roughness ranging from about 1 nm to about 2 nm.
18 . The method as recited in claim 9 wherein creating a capacitor first electrode includes creating a capacitor first electrode having a thickness ranging from about 15 nm to about 70 nm.
19 . An integrated circuit, comprising:
transistors located over a substrate, wherein at least one of said transistors includes a gate electrode stack comprising a recrystallized polysilicon layer located over a gate electrode layer; a capacitor located on said recrystallized polysilicon layer, said capacitor including;
a first electrode;
an insulator located over said first electrode; and
a second electrode located over said insulator; and
an interlevel dielectric layer located over said substrate, said interlevel dielectric layer having interconnects located therein for contacting at least one of said gate electrode stack or said capacitor.
20 . The integrated circuit as recited in claim 18 wherein at least a portion of said recrystallized polysilicon layer forms a portion of said first electrode.
21 . The integrated circuit as recited in claim 18 wherein said transistors are selected from the group consisting of:
a CMOS transistor; a bipolar transistor; and a biCMOS transistor.Join the waitlist — get patent alerts
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