Thin film transistor, method of fabricating the same, and flat panel display using the thin film transistor

Abstract

A thin film transistor with a GOLDD structure may include an active layer formed on an insulating substrate including source/drain regions and a channel region. A gate insulating film may be formed on the active layer and a gate electrode may be formed on the gate insulating film. The gate electrode may include a first gate pattern and a second gate pattern formed at sides of the first gate pattern. The source/drain regions may each have an LDD region, and the LDD regions may overlaps-the gate electrode.

1 . A thin film transistor, comprising: 
 an active layer formed on an insulating substrate and having source/drain regions and a channel region;    a gate insulating film formed on the active layer; and    a gate electrode formed on the gate insulating film, and comprising a first gate pattern and a second gate pattern formed at sides of the first gate pattern,    wherein each of the source/drain regions comprises an LDD region, and the LDD regions overlap the gate electrode.    
     
     
         2 . The thin film transistor of  claim 1 , wherein the second gate pattern has a tapered angle.  
     
     
         3 . The thin film transistor of  claim 2 , wherein the tapered angle is created by anisotropic etching.  
     
     
         4 . The thin film transistor of  claim 1 , wherein the second gate pattern is about 2 μm or less wide.  
     
     
         5 . The thin film transistor of  claim 1 , wherein the second gate pattern is about 1 μm or less wide.  
     
     
         6 . The thin film transistor of  claim 1 , wherein the LDD region lies under the second gate pattern.  
     
     
         7 . The thin film transistor of  claim 1 , wherein the LDD region is narrower than the second gate pattern.  
     
     
         8 . The thin film transistor of  claim 1 , wherein the LDD region is about 2 μm or less wide.  
     
     
         9 . The thin film transistor of  claim 1 , wherein the LDD region is about 1 μm or less wide.  
     
     
         10 . A method of fabricating a thin film transistor, comprising: 
 forming an active layer on an insulating substrate;    forming a gate insulating film on the active layer;    forming a first gate pattern on the gate insulating film;    lightly doping the active layer, using the first gate pattern as mask;    forming a second gate pattern formed at sides of the first gate pattern, wherein the first gate pattern and the second gate pattern taken together form a gate electrode; and    highly doping the active layer, using the gate electrode as mask,    wherein highly doping creates source/drain regions, the source/drain regions have LDD regions, and the LDD regions overlap the gate electrode.    
     
     
         11 . The method of  claim 10 , wherein forming the second gate pattern comprises: 
 forming a conductive material film on substantially an entire surface of the insulating substrate having the first gate pattern; and    etching the conductive material film.    
     
     
         12 . The method of  claim 10 , wherein the second gate pattern is about 2 μm or less wide.  
     
     
         13 . The method of  claim 10 , wherein the second gate pattern is about 1 μm or less wide.  
     
     
         14 . The method of  claim 10 , wherein the LDD region lies under the second gate pattern.  
     
     
         15 . The method of  claim 10 , wherein the LDD region is narrower than the second gate pattern.  
     
     
         16 . The method of  claim 10 , wherein the LDD region is about 2 μm or less wide.  
     
     
         17 . The method of  claim 16 , wherein the LDD region is about 1 μm or less wide.  
     
     
         18 . A method for fabricating a thin film transistor, comprising: 
 forming an active layer on an insulating substrate;    forming a gate insulating film on the active layer;    forming a first gate pattern on the gate insulating film;    forming a second gate pattern at sides of the first gate pattern, wherein the second gate pattern has a tapered angle; and    doping on the active layer, using the gate electrode as a mask,    wherein doping creates source/drain regions that each have an LDD region, and the LDD regions overlaps the gate electrode.    
     
     
         19 . The method of  claim 18 , wherein forming the second gate pattern comprises: 
 forming a conductive material film on substantially an entire surface of the insulating substrate having the first gate pattern; and    etching the conductive material film by anisotropic etching.    
     
     
         20 . The method of  claim 18 , wherein the second gate pattern is about 2 μm or less wide.  
     
     
         21 . The method of  claim 20 , wherein the second gate pattern is about 1 μm or less wide.  
     
     
         22 . The method of  claim 18 , wherein the LDD region is formed during the doping.  
     
     
         23 . The method of  claim 18 , wherein the LDD is narrower than the second gate pattern.  
     
     
         24 . The method of  claim 18 , wherein the LDD region is about 2 μm or less wide.  
     
     
         25 . The method of  claim 24 , wherein the LDD region is about 1 μm or less wide.  
     
     
         26 . An active matrix flat panel display using a thin film transistor, wherein the thin film transistor comprises: 
 an active layer formed on an insulating substrate and having source/drain regions and a channel region;    a gate insulating film formed on the active layer; and    a gate electrode formed on the gate insulating film, and comprising a first gate pattern and a second gate pattern formed at sides of the first gate pattern,    wherein each of the source/drain regions comprises an LDD region, and the LDD regions overlap the gate electrode.    
     
     
         27 . The active matrix flat panel display of  claim 26 , wherein the flat panel display is a liquid crystal display or an organic electroluminescent display.