Method of fabricating CMOS inverter and integrated circuits utilizing strained surface channel MOSFETs

Abstract

A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si 1-x Ge x layer on the Si substrate, and a strained surface layer on said relaxed Si 1-x Ge x layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si 1-x Ge x layer on the Si substrate, and a strained layer on the relaxed Si 1-x Ge x layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

1 - 43 . (canceled)  
     
     
         44 . A method of fabricating a circuit comprising the steps of: 
 providing a structure comprising a substrate, the structure having a surface roughness of less than 1 nm;    adding a strain-inducing material to the structure; and    integrating a pMOSFET and an nMOSFET in the structure,    wherein a channel of the pMOSFET and a channel of the nMOSFET are each strained and the strain in at least one of the strained channels is induced by the strain-inducing material.    
     
     
         45 . The method of  claim 44 , wherein at least one of the strained channels in which the strain is induced by the strain-inducing material comprises silicon.  
     
     
         46 . The method of  claim 44 , further comprising: 
 providing a device isolation region for at least one of the pMOSFET and the nMOSFET.    
     
     
         47 . The method of  claim 46 , wherein at least one device isolation region is proximate a material comprising SiGe.  
     
     
         48 . The method of  claim 47 , wherein the material comprising SiGe is at least partially relaxed.  
     
     
         49 . The method of  claim 44 , wherein the strain-inducing material comprises silicon.  
     
     
         50 . The method of  claim 49 , further comprising: 
 providing a device isolation region for at least one of the pMOSFET and nMOSFET.    
     
     
         51 . The method of  claim 50 , wherein the device isolation region is proximate the strain-inducing material.  
     
     
         52 . The method of  claim 44 , wherein the strain-inducing material comprises germanium.  
     
     
         53 . The method of  claim 52 , further comprising: 
 providing a device isolation region for at least one of the pMOSFET and NMOSFET.    
     
     
         54 . The method of  claim 53 , wherein the strain-inducing material is proximate the device isolation region.  
     
     
         55 . The method of  claim 44 , wherein the strain-inducing material is at least partially relaxed.  
     
     
         56 . The method of  claim 44 , wherein the structure comprises an insulator layer and at least one of the strained channels is disposed over the insulator layer.  
     
     
         57 . The method of  claim 44 , wherein the pMOSFET and nMOSFET are interconnected to form an inverter.  
     
     
         58 . The method of  claim 44 , wherein the pMOSFET and nMOSFET are interconnected to form a logic gate.  
     
     
         59 . The method of  claim 58 , wherein the logic gate is a NOR gate.  
     
     
         60 . The method of  claim 58 , wherein the logic gate is an XOR gate.  
     
     
         61 . The method of  claim 58 , wherein the logic gate is a NAND gate.  
     
     
         62 . The method of  claim 44 , wherein the pMOSFET serves as a pull-up transistor in a CMOS circuit and the nMOSFET serves as a pull-down transistor in a CMOS circuit.