Semiconductor device and method of manufacturing the same

Abstract

There are provided a bleeder resistance circuit which has an accurate voltage dividing ratio, a small temperature coefficient of a resistance value, and high precision, and a semiconductor device using such a bleeder resistance circuit, which has high precision and a small temperature coefficient, such as a voltage detector or a voltage regulator. In the bleeder resistance circuit using a thin film resistor, conductors located over and under the thin film resistor are made to have substantially the same potential as the thin film resistor. Further, when polysilicon is used for the thin film resistor, the film thickness of the polysilicon thin film resistor is thinned, and an impurity introduced into the polysilicon thin film resistor is made to be a P-type. Thus, a variation in a resistance value is suppressed, and a temperature dependency of the resistance value is made small.

1 - 31 . (canceled)  
   
   
       32 . A method of manufacturing a semiconductor device, comprising the steps of: 
 preparing a silicon substrate to form a plurality of selectively separated and independent well regions by an ion implantation method;    selectively forming a field oxide film by the LOCOS method in the surface of the silicon substrate;    forming a gate oxide film, performing a channel dope for a predetermined threshold control, depositing a polysilicon layer by a CVD method, and selectively introducing an impurity into the polysilicon layer by an ion implantation method so as to obtain a predetermined sheet resistance value;    after selectively introducing an impurity such as phosphorus with a high concentration into the polysilicon layer such that a predetermined region of the polysilicon layer has a low resistance, processing the polysilicon layer by etching into a predetermined shape such that a gate electrode with a low resistance and a plurality of polysilicon resistors each having a high resistance region are matched with the well regions, and locating the gate electrode and the polysilicon resistors;    introducing an N-type impurity such as phosphorus by an ion implantation method to form a source region and a drain region of an N-type transistor;    introducing a P-type impurity by an ion implantation method to form a source region and a drain region of a P-type transistor and a low resistance region of each of the polysilicon resistors;    depositing an intermediate insulating film, and subsequently forming a contact hole;    depositing an aluminum layer as a wiring by a sputtering method, and then patterning the aluminum layer such that the aluminum layer connected with the low resistance region in one end of each of the polysilicon resistors and each of the well regions is located on each of the polysilicon resistors; and    forming a protective film, and removing a portion of the protective film to provide a region of a bonding pad and the like.    
   
   
       33 . A method of manufacturing a semiconductor device, comprising the steps of: 
 preparing a silicon substrate to form a plurality of selectively separated and independent well regions by an ion implantation method, and selectively forming a field oxide film by the LOCOS method;    after forming a gate oxide film, performing a channel dope for a predetermined threshold control, depositing a first polysilicon layer by a CVD method, and introducing an impurity such as phosphorus with a high concentration into the first polysilicon layer such that the first polysilicon layer has a low resistance;    processing the first polysilicon layer by etching into a predetermined shape to form a gate electrode with a low resistance and a plurality of low resistance polysilicon layers;    forming a first insulating film by a thermal oxidation method or a CVD method;    depositing a second polysilicon layer with a film thickness thinner than that of the first polysilicon layer, and introducing an impurity into the second polysilicon layer by an ion implantation method so as to obtain a predetermined sheet resistance value;    patterning the second polysilicon layer such that a plurality of polysilicon resistors using the second polysilicon layer are formed on the independent low resistance polysilicon layers through the first insulating film;    introducing an N-type impurity by an ion implantation method to form a source region and a drain region of a P-type transistor together with a low resistance region in a portion of each of the polysilicon resistors;    depositing an intermediate insulating film, and forming a common contact hole such that the low resistance region of each of the polysilicon resistors and each of the low resistance polysilicon layers can be connected with each other through the common contact hole;    depositing an aluminum layer as a wiring by a sputtering method, and patterning the aluminum layer such that the aluminum layer for connecting, the low resistance region in one end of each of the polysilicon resistors, with each of the low resistance polysilicon layers located under each of the polysilicon resistors through the first insulating film, through the common contact hole, is located on each of the polysilicon resistors; and    forming a protective film, and removing a portion of the protective film to provide a region of a bonding pad and the like.