Semiconductor device and method for fabricating the same

Abstract

Disclosed is a semiconductor device having a double dielectric layer, wherein the double dielectric layer comprises a first dielectric layer having aluminum and a second dielectric layer, of which a dielectric constant is higher than that of the first dielectric layer, stacked on the first dielectric layer. Also disclosed are methods for fabricating the semiconductor device.

1 . A semiconductor device having a double dielectric layer, wherein the double dielectric layer comprises; 
 a first dielectric layer having aluminum; and    a second dielectric layer stacked on the first dielectric layer, said second dielectric layer having a dielectric constant higher than that of the first dielectric layer.    
   
   
       2 . The semiconductor device as recited in  claim 1 , wherein the first dielectric layer is an Al 2 O 3  layer.  
   
   
       3 . The semiconductor device as recited in  claim 1 , wherein the second dielectric layer is formed with a layer selected from the group consisting of an oxide layer having tantalum, an oxide layer having a perovskite structure and a combination thereof.  
   
   
       4 . The semiconductor device as recited in  claim 3 , wherein the oxide layer having tantalum is a TaON layer, a Ta 2 O 5  layer or a BST layer.  
   
   
       5 . A semiconductor device comprising: 
 a semiconductor substrate;    a first gate electrode on the semiconductor substrate;    a first gate insulating layer comprising aluminum on said first gate electrode;    a second gate insulating layer stacked on the first insulating layer, said second dielectric layer having a dielectric constant higher than that of the first gate insulating layer; and    a second gate electrode on the second gate insulating layer.    
   
   
       6 . The semiconductor device as recited in  claim 5 , wherein the first gate insulating layer comprises an Al 2 O 3  layer.  
   
   
       7 . The semiconductor device as recited in  claim 5 , wherein the second gate insulating layer is formed of a layer selected from the group consisting of a TaON layer, a Ta 2 O 5  layer and a BST layer.  
   
   
       8 . The semiconductor device as recited in  claim 5 , wherein the first and second gate electrodes are formed with a silicon layer having at least a doped polysilicon layer or a doped amorphous silicon layer, a metal layer having at least TiN, TaN, W, WN, Ru, Ir or Pt or a silicide layer having at least CoSi, MoSi or WSi.  
   
   
       9 . The semiconductor device as recited in  claim 5 , further comprising a nitride layer between the first gate electrode and the first gate insulating layer.  
   
   
       10 . The semiconductor device as recited in  claim 5 , wherein the first gate insulating layer is formed at a thickness of 10 Å to 20 Å.  
   
   
       11 . The semiconductor device as recited in  claim 5 , wherein the second gate insulating layer is formed at a thickness of 50 Å to 100 Å.  
   
   
       12 . The semiconductor device as recited in  claim 5 , wherein the surface of the first gate electrode is uneven.  
   
   
       13 - 29 . (canceled)