Method of depositing barrier layer from metal gates

Abstract

A method of manufacturing a high performance MOS device and transistor gate stacks comprises forming a gate dielectric layer over a semiconductor substrate; forming a barrier layer over the gate dielectric layer by an ALD type process; and forming a gate electrode layer over the barrier layer. The method enables the use of hydrogen plasma, high energy hydrogen radicals and ions, other reactive radicals, reactive oxygen and oxygen containing precursors in the processing steps subsequent to the deposition of the gate dielectric layer of the device. The ALD process for forming the barrier layer is performed essentially in the absence of plasma and reactive hydrogen radials and ions. This invention makes it possible to use oxygen as a precursor in the deposition of the metal gates. The barrier film also allows the use of hydrogen plasma in the form of either direct or remote plasma in the deposition of the gate electrode. Furthermore, the barrier film prevents the electrode material from reacting with the gate dielectric material. The barrier layer is ultra thin and, at the same time, it forms a uniform cover over the entire surface of the gate dielectric.

1 . A gate stack in an integrated circuit comprising a dielectric layer, a gate electrode and a barrier layer located between the dielectric layer and the gate electrode, wherein the barrier layer is composed of a different material than the gate electrode and wherein the gate dielectric comprises a metal oxide and the barrier layer comprises the same metal and nitrogen.  
   
   
       2 . The gate stack of  claim 1 , wherein the metal is Hf.  
   
   
       3 . The gate stack of  claim 1 , wherein the barrier layer further comprises another element selected from the group consisting of Group IV elements and other metals.  
   
   
       4 . The gate stack of  claim 3 , wherein the barrier layer is comprised of a material selected from the group consisting of HfN, TaN, HfSi x N y , TiSi x N y , TaSi x N y , WN x C y , and HfAl x N y .  
   
   
       5 . The gate stack of  claim 4 , wherein the barrier layer is comprised of a material selected from the group consisting of HfN and WN x C y .  
   
   
       6 . The gate stack of  claim 1 , wherein the barrier layer has a thickness of less than 80 Å.  
   
   
       7 . The gate stack of  claim 1 , wherein the barrier layer has a thickness small enough not to affect a work function of the gate stack.  
   
   
       8 . The gate stack of  claim 1 , wherein the barrier layer has a thickness of between about 1 and 50 molecular layers.  
   
   
       9 . The gate stack of  claim 1 , wherein the barrier layer has a thickness of between about 2 and 20 molecular layers.  
   
   
       10 . The gate stack of  claim 1 , wherein the barrier layer has a thickness of between about 2 and 4 molecular layers.  
   
   
       11 . The gate stack of  claim 1 , wherein the barrier layer is conductive.  
   
   
       12 . The gate stack of  claim 1 , wherein the gate electrode is comprised of a material selected from the group consisting of polysilicon, poly-SiGE, W, TiN, TaN, Al, Ni, and Ti.  
   
   
       13 . The gate stack of  claim 1 , wherein the gate dielectric is a high k material.  
   
   
       14 . The gate stack of  claim 13 , wherein the high k material has a dielectric constant greater than 5.  
   
   
       15 . The gate stack of  claim 13 , wherein the gate dielectric is comprised of a material selected from the group consisting of HfO 2 , ZrO 2 , TiO 2 , Ta 2 O 5 , strontium titanate (ST), barium titanate (BT), barium strontium titanate (BST), lead zirconium titanate (PZT) and strontium bismuth tantalite (SBT).  
   
   
       16 . The gate stack of  claim 13 , wherein the gate dielectric comprises a laminate of multiple layers.  
   
   
       17 . A gate stack in an integrated circuit comprising a substrate, a high k dielectric layer, a gate electrode and a barrier layer located between the dielectric layer and the gate electrode, wherein the barrier layer has a thickness between 2 and 20 molecular layers.  
   
   
       18 . The gate stack of  claim 17 , additionally comprising an interfacial layer between the substrate and the high k dielectric layer.  
   
   
       19 . The gate stack of  claim 18 , wherein the interfacial layer is about 5 Å thick.  
   
   
       20 . The gate stack of  claim 18 , wherein the interfacial layer comprises a native oxide.  
   
   
       21 . The gate stack of  claim 18 , wherein the interfacial layer comprises a material selected from the group consisting of aluminum oxide and lanthanide oxides.  
   
   
       22 . The gate stack of  claim 17 , wherein the barrier layer has a thickness between 2 and 4 molecular layers.  
   
   
       23 . The gate stack of  claim 17 , wherein the barrier layer comprises a nanolaminate structure.  
   
   
       24 . The gate stack of  claim 17 , wherein the high k material comprises HfO 2 .  
   
   
       25 . The gate stack of  claim 24 , wherein the barrier layer comprises HfN.  
   
   
       26 . The gate stack of  claim 17 , wherein the substrate comprises a material selected from the group consisting of silicon and GaAs.  
   
   
       27 . The gate stack of  claim 17 , wherein the substrate is an epitaxial layer.  
   
   
       28 . The gate stack of  claim 17 , wherein the barrier layer is thicker than the dielectric layer.