Method of forming minimally spaced word lines

Abstract

A method of forming minimally spaced word lines is disclosed. A double exposure technique is employed at the gate formation level. A small trench is defined through gate stack layers by using a tapered etch or spacers to achieve the desired width of the trench. A filler material fills the trench and forms a filler plug. The gate layers adjacent to the trench are then patterned and etched and the filler plug is removed to obtain gate stacks spaced apart by a distance of less than about 400 Angstroms.

1 - 74 . (canceled)  
   
   
       75 . An integrated circuit structure, comprising: 
 a semiconductor substrate;    an oxide layer over said semiconductor substrate;    a polysilicon layer over said oxide layer;    an insulating layer over said polysilicon layer, said insulating layer having a first opening within said insulating layer, said first opening having a width not greater than about 400 Angstroms; and    a photoresist layer over said insulating layer, said photoresist layer having a second opening within said photoresist layer, said second opening being in communication with said first opening and having a width not greater than about 4,000 Angstroms.    
   
   
       76 . An integrated circuit structure, comprising: 
 a semiconductor substrate;    at least one isolation region formed within said semiconductor substrate; and    at least two gate stacks over said semiconductor substrate, said at least two gate stacks being in contact with said isolation region and being spaced apart from each other by less than about 300 Angstroms.    
   
   
       77 . A memory structure comprising: 
 a semiconductor substrate; and    at least two word lines over said semiconductor substrate, said at least two word lines being spaced from each other by less than about 300 Angstroms.    
   
   
       78 . The memory structure of  claim 77  further comprising a plurality of bit lines formed over and in contact with said at least two word lines.  
   
   
       79 . The memory structure of  claim 77  further comprising an isolation region formed below said at least two word lines being spaced apart from each other.  
   
   
       80 . The memory structure of  claim 77 , wherein each of said at least two word lines further comprises a plurality of gate layers.  
   
   
       81 . The memory structure of  claim 80 , wherein each of said at least two word lines includes a polysilicon layer.  
   
   
       82 . The memory structure of  claim 80 , wherein each of said at least two word lines includes a metal silicide layer.  
   
   
       83 . The memory structure of  claim 77 , wherein said memory structure is a DRAM structure.  
   
   
       84 . The memory structure of  claim 77 , wherein said memory structure is a SRAM structure.  
   
   
       85 . A memory device comprising a plurality of DRAM cells, said DRAM cells including a plurality of word lines formed over a semiconductor substrate, at least two of said plurality of word lines being spaced apart from each other by less than about 300 Angstroms, and a plurality of bit lines formed over said plurality of word lines.  
   
   
       86 . The memory device of  claim 85  further comprising an isolation region formed below and in contact with said at least two of said plurality of word lines being spaced apart from each other.