Circuit group control system

Abstract

A circuit group control system which receives from a master processor a first command sequence and a second command sequence each of which is composed of a plurality of commands, each command being to be executed by one of a plurality of circuits, and causes any available circuits to execute the commands one by one in order of arrangement in each command sequence. The circuit group control system achieves concurrent execution of a plurality of command sequences by causing a circuit (a second circuit) to execute a command in the second command sequence while another circuit (a first circuit) is executing another command in the first command sequence.

1 - 23 . (canceled)  
   
   
       24 . A circuit group control system for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising: 
 a command sequence specification receiving unit operable to receive from the master processor specification of a plurality of command sequences each of which is composed of a plurality of commands, each command being to be executed by one of the plurality of circuits; and    an execution control unit operable to cause any available circuits among the plurality of circuits to execute the plurality of commands in each command sequence one by one in order of arrangement, wherein    the command sequence specification receiving unit includes a command storage memory, and recognizes the specification of the plurality of command sequences when the master processor writes the plurality of commands for each command sequence into the command storage memory, and    the execution control unit causes any available circuits among the plurality of circuits to execute the plurality of commands for each command sequence stored in the command storage memory, one by one in order of arrangement in each command sequence.    
   
   
       25 . The circuit group control system of  claim 24 , wherein 
 each command stored in the command storage memory has a pointer indicating a location in the command storage memory of a next command that is to be executed next to the command in a same command sequence, and    the execution control unit causes any available circuits among the plurality of circuits to execute the plurality of commands one by one in order of arrangement, by referring to the pointer in each command to recognize the location in the command storage memory of the next command.    
   
   
       26 . The circuit group control system of  claim 24  further comprising the plurality of circuits, wherein 
 each command contains a parameter,    the command storage memory is connected to one or more circuits among the plurality of circuits, and    when one of the one or more circuits is instructed by the execution control unit to execute a command, the instructed circuit accesses a parameter in the command stored in the command storage memory.    
   
   
       27 . The circuit group control system of  claim 24 , wherein 
 the specification of a command sequence is made by a command sequence identifier that identifies the command sequence composed of the plurality of commands stored in the command storage memory, and    the execution control unit causes any available circuits among the plurality of circuits to execute the plurality of commands in the command sequence that is identified by the command sequence identifier, one by one in order of arrangement in the command sequence.    
   
   
       28 . The circuit group control system of  claim 27 , wherein 
 the command sequence identifier is a pointer indicating a location of a command in the command storage memory, and    the execution control unit recognizes the command at the location indicated by the pointer as a first command in a command sequence, and causes any available circuits among the plurality of circuits to execute the plurality of commands one by one in order of arrangement in the command sequence, starting with the command at the location indicated by the pointer.    
   
   
       29 . The circuit group control system of  claim 27 , wherein 
 the command sequence specification receiving unit includes a first FIFO buffer for storing command sequence identifiers,    the master processor, after writing a plurality of commands into the command storage memory, writes command sequence identifiers into the first FIFO buffer, the command sequence identifiers identifying command sequences composed of commands among the plurality of commands, the command sequence specification receiving unit thereby recognizing specification of the command sequences, and    the execution control unit causes any available circuits among the plurality of circuits to execute commands in each of the command sequences identified by the command sequence identifiers in the first FIFO buffer.    
   
   
       30 . The circuit group control system of  claim 29 , wherein 
 the command sequence specification receiving unit further includes a second FIFO buffer for storing command sequence identifiers,    the master processor, after writing a plurality of commands into the command storage memory, writes command sequence identifiers into the second FIFO buffer, the command sequence identifiers identifying command sequences composed of commands among the plurality of commands, the command sequence specification receiving unit thereby recognizing specification of the command sequences, and    the execution control unit causes any available circuits among the plurality of circuits to execute commands in each of the command sequences identified by the command sequence identifiers in the second FIFO buffer, taking precedence over commands in each of the command sequences identified by the command sequence identifiers in the first FIFO buffer.    
   
   
       31 . The circuit group control system of  claim 24  further comprising 
 a command updating unit operable to update the commands stored in the command storage memory.    
   
   
       32 . A circuit group control system for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising: 
 a command sequence specification receiving unit operable to receive specification of a plurality of command sequences from the master processor, each command sequence being composed of a plurality of commands, each command being to be executed by one of the plurality of circuits;    an execution control unit operable to cause any available circuits among the plurality of circuits to execute the plurality of commands for each command sequence one by one in order of arrangement in each command sequence;    a completion notification request receiving unit operable to receive from the master processor a request to send a notification of completion of execution of a command; and    a completion notifying unit operable to, if having received from a circuit a notification of completion of execution of the command of which the master processor had requested to send a notification of completion of execution, send the notification to the master processor.    
   
   
       33 - 35 . (canceled)  
   
   
       36 . A circuit group control method for controlling a plurality of circuits in accordance with an instruction by a master processor, comprising: 
 a command sequence specification receiving step for receiving, from the master processor, specification of a plurality of command sequences each of which is composed of a plurality of commands, each command being to be executed by one of the plurality of circuits; and    an execution control step for causing any available circuits among the plurality of circuits to start executing corresponding commands among the plurality of commands one by one in order of arrangement in each command sequence.    
   
   
       37 . (canceled)