Test system with interconnect having conductive members and contacts on opposing sides

Abstract

A method for fabricating semiconductor components and interconnects includes the steps of providing a substrate, such as a semiconductor die, forming external contacts on opposing sides of the substrate by laser drilling vias through the substrate, and forming conductive members in the vias. The conductive members include enlarged terminal portions that are covered with a non-oxidizing metal. The method can be used to fabricate stackable semiconductor packages having integrated circuits in electrical communication with the external contacts. The method can also be used to fabricate interconnects for electrically engaging packages, dice and wafers for testing or for constructing electronic assemblies.

1 - 43 . (canceled)  
   
   
       44 . A system for testing a semiconductor component having a bumped contact comprising: 
 a test circuitry configured to apply test signals to the component;    a substrate comprising a first side and an opposing second side;    a via through the substrate;    a conductive member in the via;    a first external contact on the first side in electrical communication with the conductive member configured to electrically engage the bumped contact; and    a second external contact on the second side in electrical communication with the conductive member configured to provide an electrical path to the test circuitry.    
   
   
       45 . The system of  claim 44  wherein the first external contact and the second external each include a non-oxidizing layer.  
   
   
       46 . The system of  claim 44  wherein the first external contact and the second external contact each comprise a terminal portion of the conductive material.  
   
   
       47 . The system of  claim 44  wherein the first external contact and the second external are offset with respect to another.  
   
   
       48 . An electronic assembly comprising: 
 an interconnect comprising: 
 a substrate having a first side and an opposing second side;  
 a via through the substrate;  
 a conductive member in the via;  
 a first external contact on the first side comprising a first non-oxidizing layer on the conductive member; and  
 a second external contact on the second side comprising a second non-oxidizing layer on the conductive member; and  
   a first semiconductor component having a bumped contact bonded to the first external contact.    
   
   
       49 . The electronic assembly of  claim 48  further comprising a second semiconductor component having a bumped contact bonded to the second external contact.  
   
   
       50 . A test system for a semiconductor component having a bumped contact comprising: 
 a testing circuitry configured to apply test signals to the component;    an interconnect comprising: 
 a substrate comprising a first side having a first electrically insulating layer thereon, and an opposing second side having a second electrically insulating layer thereon;  
 a via through the substrate;  
 a conductive member in the via;  
 a first external contact on the first electrically insulating layer comprising a concave terminal portion of the conductive member configured to electrically engage the bumped contact; and  
 a second external contact on the second electrically insulating layer in electrical communication with the conductive member configured to provide an electrical path to the test circuitry.  
   
   
   
       51 . The test system of  claim 50  wherein the component comprises a semiconductor die or a semiconductor package.  
   
   
       52 . The test system of  claim 51  further comprising a force applying mechanism on the interconnect configured to bias the bumped contact and the first external contact together.  
   
   
       53 . The test system of  claim 50  wherein the component comprises a semiconductor wafer.  
   
   
       54 . The test system of  claim 52  further comprising a spring loaded electrical connector in electrical communication with the testing circuitry and in physical contact with the second external contact.  
   
   
       55 . The test system of  claim 54  wherein the second external contact comprises a second concave terminal portion configured to physically contact the electrical connector.  
   
   
       56 . A system for testing a semiconductor component having bumped contacts comprising: 
 a test circuitry configured to apply test signals to the component;    a plurality of electrical connectors in electrical communication with the test circuitry; and    an interconnect comprising a substrate having a first side and an opposing second side, a plurality of vias in the substrate, and a plurality of conductive members in the vias having first terminal portions on the first side configured to electrically engage the bumped contacts and second terminal portions on the second side configured to electrically engage the electrical connectors.    
   
   
       57 . The system of  claim 56  further comprising first non-oxidizing layers on the first terminal portions and second non-oxidizing layers on the second terminal portions.  
   
   
       58 . The system of  claim 56  wherein each first terminal portion has a generally concave shape.  
   
   
       59 . The system of  claim 56  wherein each second terminal portion has a generally concave shape.  
   
   
       60 . The system of  claim 56  wherein the component is contained on a wafer comprising a plurality of components.  
   
   
       61 . The system of  claim 60  wherein the interconnect is configured to electrically engage all of the components on the wafer.  
   
   
       62 . The system of  claim 56  wherein the electrical connectors comprise spring loaded connectors.  
   
   
       63 . The system of  claim 56  wherein the electrical connectors are mounted to a testing apparatus comprising a wafer probe handler or a probe tester.  
   
   
       64 . A system for testing a semiconductor component having bumped contacts comprising: 
 a test circuitry configured to apply test signals to the component;    an interconnect comprising a substrate having a first side and an opposing second side, a plurality of vias in the substrate, and a plurality of conductive members in the vias having first terminal portions on the first side configured to electrically engage the bumped contacts and second terminal portions on the second side configured to electrically engage the electrical connectors;    an alignment member on the interconnect configured to align the bumped contacts to the first terminal portions; and    a force applying mechanism on the interconnect configured to bias the bumped contacts and the first terminal portions together.    
   
   
       65 . The system of  claim 64  further comprising first non-oxidizing layers on the first terminal portions and second non-oxidizing layers on the second terminal portions.  
   
   
       66 . The system of  claim 64  wherein each first terminal portion has a generally concave shape.  
   
   
       67 . The system of  claim 64  wherein each second terminal portion has a generally concave shape.  
   
   
       68 . The system of claim wherein the component comprises a semiconductor die or a semiconductor package.  
   
   
       69 . The system of  claim 64  further comprising a plurality of terminal contacts on the second terminal portions comprising balls or bumps.