Substrate with stacked vias and fine circuits thereon, and method for fabricating the same

Abstract

A substrate with stacked vias and fine circuits and a method for fabricating the substrate are proposed. A core layer is formed with a metal layer respectively on upper and lower surfaces thereof, and at least one through hole. A first insulating layer is applied over the metal layer on the upper surface of the core layer and selectively formed with at least one first opening for exposing the metal layer. A metal layer is formed within the first opening, and a second insulating layer is applied over the first insulating layer and formed with a plurality of second openings, wherein the metal layer within the first opening is exposed via at least one second opening. After a conductive layer is applied over the second insulating layer and within the second openings, a metal layer is formed within the second openings. Finally, the conductive layer is removed by micro-etching.

1 - 5 . (canceled)  
     
     
         6 . A substrate with stacked vias and fine circuits, comprising: 
 a core layer including an upper surface, an opposing lower surface, a patterned circuit layer respectively formed on the upper and lower surfaces of the core layer, and at least one conductive through hole for providing electrical connection between the circuit layers;    at least one first insulating layer applied over the circuit layer on the upper surface of the core layer and selectively formed with at least one first opening for exposing a portion of the circuit layer underneath the first insulating layer, wherein a metal layer is formed within the first opening;    at least one second insulating layer applied over the first insulating layer and selectively formed with a plurality of second openings, wherein the metal layer formed within the first opening is exposed via at least one of the second openings;    a conductive layer applied within the second openings; and    a metal layer formed within the second openings and electrically connected to the circuit layer within the first opening to form a stacked via.    
     
     
         7 . The substrate of  claim 6 , wherein the metal layer formed within the second opening is a conductive trace.  
     
     
         8 . The substrate of  claim 6 , wherein the metal layer formed within the second opening is a conductive via.  
     
     
         9 . The substrate of  claim 6 , wherein each of the first and second insulating layers is a photoimageable insulating layer.  
     
     
         10 . The substrate of  claim 9 , wherein the photoimageable insulating layer is selectively formed with at least one opening using photolithography technology.  
     
     
         11 . The substrate of  claim 9 , wherein the photoimageable insulating layer is made of photoimageable polymer.