Method and system for minimizing differential amplifier power supply sensitivity

Abstract

The invention includes an apparatus and a method for minimizing power supply sensitivity of a differential amplifier. The apparatus includes a current source providing a differential amplifier bias current to a common source node of the differential amplifier. A voltage sensor senses variations of a power supply associated with the current source. Variations sensed by the voltage sensor control a magnitude of the differential amplifier bias current. The method includes a current source providing the source current. A voltage potential of the common source node is sensed. The current source is adjusted depending upon the sensed voltage potential of the common source node, thereby adjusting a magnitude of the source current.

1 - 16 . (canceled)  
     
     
         17 . A method for minimizing power supply sensitivity of a differential amplifier, the differential amplifier conducting a source current at a common source node, the method comprising: 
 a current source providing the source current;    sensing a voltage potential of the common source node;    adjusting the current source depending upon the sensed voltage potential of the common source node, thereby adjusting a magnitude of the source current.    
     
     
         18 . The method for minimizing power supply sensitivity of a differential amplifier of  claim 17 , wherein the current source comprises a current mirror, adjusting the current source comprises adjusting a bias current of the current mirror.  
     
     
         19 . The method for minimizing power supply sensitivity of a differential amplifier of  claim 18 , wherein the current mirror comprises an amplifier bias current transistor and a mirror transistor.  
     
     
         20 . The method for minimizing power supply sensitivity of a differential amplifier of  claim 19 , wherein adjusting the current source comprises adjusting at least one of an amplifier bias current transistor back gate bias, and a mirror transistor back gate bias.  
     
     
         21 . The method for minimizing power supply sensitivity of a differential amplifier of  claim 19 , wherein adjusting the current source comprises adjusting characteristics of the amplifier bias current transistor.  
     
     
         22 . The method for minimizing power supply sensitivity of a differential amplifier of  claim 21 , wherein the amplifier bias current transistor comprises a plurality of sub-bias current transistors, and adjusting characteristics of the amplifier bias current transistor comprises controlling an inclusion of a number of parallel sub-bias current transistors, wherein each included sub-bias current transistors contributes to the differential amplifier bias current.  
     
     
         23 . The method for minimizing power supply sensitivity of a differential amplifier of  claim 21 , wherein the amplifier bias current transistor comprises a plurality of sub-bias current transistors, and adjusting characteristics of the amplifier bias current transistor comprises adjusting a bias of the parallel bias current transistor, wherein the parallel bias current transistor contributes to the differential amplifier bias current.  
     
     
         24 . (canceled)  
     
     
         25 . (canceled)