Semiconductor device and its test method

Abstract

A second semiconductor chip including the operation of receiving operation instructions given from a first semiconductor chip and outputting a signal corresponding to it is mounted on mounting means. Internal wirings for interconnecting the first and second semiconductor chips, and external terminals respectively connected to the internal wirings are provided in the mounting means to constitute a multi chip module. Further, a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip is provided inside the module.

1 . A semiconductor device, comprising: 
 a first semiconductor chip;    a second semiconductor chip including the operation of receiving instructions as to an operation from the first semiconductor chip and outputting a signal corresponding thereto; and    mounting means having a plurality of internal wirings and a plurality of external terminals, said mounting means being equipped with the first semiconductor chip and the second semiconductor chip with a state of both being electrically connected to the internal wirings, and having internal wirings for interconnecting the first and second semiconductor chips with each other, external terminals respectively connected to the internal wirings, and external terminals connected to the first or second semiconductor chip;    said semiconductor device being provided with a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip.    
   
   
       2 . The semiconductor device according to  claim 1 , 
 wherein a transfer path for instructions given from the first semiconductor chip has a first internal wiring connected to the first semiconductor chip, a first external terminal connected to the first internal wiring, a second internal wiring connected to the second semiconductor chip, and a second external terminal connected to the second internal wiring, and    wherein a signal path for selectively validating and invalidating operation instructions from the first semiconductor chip to the second semiconductor chip in accordance with the presence or absence of a connection between the first and second external terminals is configured.    
   
   
       3 . The semiconductor device according to  claim 1 , wherein the second semiconductor chip has a control terminal for neglecting the operation instructions given from the first semiconductor chip, and the control terminal is connected to the corresponding external terminal.  
   
   
       4 . The semiconductor device according to  claim 1 , wherein the first and second semiconductor chips have control terminals for validating/invalidating their operations, and the control terminals are respectively connected to the external terminals.  
   
   
       5 . The semiconductor device according to  claim 1 , 
 wherein the first semiconductor chip is a processor including a central processing unit, and    wherein the second semiconductor chip is a memory circuit.    
   
   
       6 . The semiconductor device according to  claim 5 , wherein the second semiconductor chip is configured in plural form and includes a random access memory and a nonvolatile memory.  
   
   
       7 . The semiconductor device according to  claim 5 , 
 wherein the first semiconductor chip is a processor including a plurality of central processing units, and a processor peripheral circuit, and    wherein the second semiconductor chip includes a plurality of random access memories and nonvolatile memories.    
   
   
       8 . The semiconductor device according to  claim 6 , wherein the first semiconductor chip or the second semiconductor chip is directed to a product which constitutes one semiconductor device by itself.  
   
   
       9 . The semiconductor device according to  claim 1 , wherein the first semiconductor chip includes a signal path for outputting a signal equivalent to the operation instructions relative to the second semiconductor chip to an external terminal instead of the operation instructions in accordance with the setting thereof to a specific operation mode.  
   
   
       10 . The semiconductor device according to  claim 9 , wherein the first semiconductor chip is a processor including a central processing unit and has a bus release function.  
   
   
       11 . The semiconductor device according to  claim 1 , 
 wherein the first semiconductor chip has a signal which holds an output state even though the first semiconductor chip is brought to a breakdown state by a disable signal, and which is connected to the second semiconductor chip, and    wherein the signal holding the output state in the breakdown state is led once to the outside of the multi chip module and set so as to be connectable and changeable outside the multi chip module, a semiconductor chip to be tested in the multi chip module is made equivalent to a semiconductor device having a single semiconductor chip under coupling control on the signal holding the output state outside the multi chip module to thereby allow a test pattern for the single semiconductor chip to be applied as it is.    
   
   
       12 . A method of testing a semiconductor device comprising: 
 a first semiconductor chip;    a second semiconductor chip including the operation of receiving instructions as to an operation from the first semiconductor chip and outputting a signal corresponding thereto; and    mounting means having a plurality of internal wirings and a plurality of external terminals, said mounting means being equipped with the first semiconductor chip and the second semiconductor chip with a state of both being electrically connected to the internal wirings, and having internal wirings for interconnecting the first and second semiconductor chips with each other, external terminals respectively connected to the internal wirings, and external terminals connected to the first or second semiconductor chip;    said semiconductor device being provided with a signal path for selectively invalidating operation instructions from the first semiconductor chip to the second semiconductor chip, and said semiconductor device being a multi chip module,    said method comprising the step of:    invalidating the operation instructions from the first semiconductor chip to the second semiconductor chip and performing an operation test directed from the first semiconductor chip to the second semiconductor chip between the first semiconductor chip and a test device connected to the external terminal.    
   
   
       13 . The method according to  claim 12 , 
 wherein the internal wiring for transferring the operation instructions from the first semiconductor chip to the second semiconductor chip is connected to a first external terminal,    wherein an internal wiring extended from a second external terminal for transferring operation instructions directed to the second semiconductor chip is connected to the second semiconductor chip,    wherein the connection between the first and second external terminals is released to selectively invalidate the operation instructions from the first semiconductor chip to the second semiconductor chip,    wherein a signal outputted from the first external terminal is supplied to the test device to thereby cause the first semiconductor chip to give operation instructions to the test device, and    wherein the second external terminal is fixed to a level which deactivates the second semiconductor chip.    
   
   
       14 . The method according to  claim 12 , 
 wherein the second semiconductor chip has a control terminal for neglecting the operation instructions given from the first semiconductor chip, said control terminal being connected to the external terminal, and    wherein the operation test directed from the first semiconductor chip to the second semiconductor chip is carried out between the first semiconductor chip and the test device connected to the external terminal.    
   
   
       15 . The method according to  claim 12 , 
 wherein the first and second semiconductor chips respectively have control terminals for validating/invalidating their operations, said control terminals being respectively connected to the external terminals, and    wherein the operation of the first semiconductor chip is invalidated to carry out the operation test directed to the second semiconductor chip between the first semiconductor chip and the test device connected to the external terminal.    
   
   
       16 . The method according to  claim 12 , 
 wherein the first semiconductor chip includes a circuit which outputs a signal equivalent to the operation instructions relative to the second semiconductor chip to a third external terminal in place of the operation instructions in accordance with the setting thereof to a specific operation mode, and    wherein the first semiconductor chip is set to the specific operation mode by the test device connected to the external terminal, and the signal outputted from the third external terminal is supplied to the test device to carry out the operation test directed from the first semiconductor chip to the second semiconductor chip between the first semiconductor chip and the test device.    
   
   
       17 . The method according to  claim 16 , 
 wherein the first semiconductor chip is a processor having a bus release function including a central processing unit, and    wherein the test device releases a bus for the processor of the first semiconductor chip to carry out the operation test directed to the second semiconductor chip by the test device.    
   
   
       18 . The method according to  claim 12 , wherein a test on connections between the first semiconductor chip or second semiconductor chip and the external terminals is carried out, and other operation tests including an operation timing test on the first semiconductor chip or the second semiconductor chip are carried out on the condition that no failure in connection occurs.