Dual metal-alloy nitride gate electrodes

Abstract

An embodiment of the invention is a gate electrode 70 having a nitrided high work function metal alloy 170 and a low work function nitrided metal alloy 190. Another embodiment of the invention is a method of manufacturing a gate electrode 70 that includes forming and then patterning and etching a layer of high work function nitrided metal alloy 170, forming a layer of low work function nitrided metal alloy 190, and then patterning and etching layers 170 and 1 90.

1 . A CMOS circuit comprising: 
 a first gate electrode having a low work function nitrided metal alloy and a high work function nitrided metal alloy; and    a second gate electrode having a high work function nitrided metal alloy.    
   
   
       2 . The CMOS circuit of  claim 1  wherein said high work function nitrided metal alloy has a majority atomic concentration of Ru.  
   
   
       3 . The CMOS circuit of  claim 1  wherein said low work function nitrided metal alloy has a majority atomic concentration of Ta.  
   
   
       4 . The CMOS circuit of  claim 1  wherein said high work function nitrided metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       5 . The CMOS circuit of  claim 1  wherein said low work function nitrided metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       6 . The CMOS circuit of  claim 1  wherein a work function of said first gate electrode is controlled by the amount of said high work function nitrided metal alloy and said low work function nitrided metal alloy.  
   
   
       7 . The CMOS circuit of  claim 1  wherein a work function of said second gate electrode is controlled by the amount of said high work function nitrided metal alloy.  
   
   
       8 . The CMOS circuit of  claim 1  wherein said first gate electrode and said second gate electrode have a thickness between 5 Å and 2500 Å.  
   
   
       9 . The CMOS circuit of  claim 1  wherein a thickness of said high work function nitrided metal alloy is different from a thickness of said low work function nitrided metal alloy.  
   
   
       10 . The CMOS circuit of  claim 1  wherein said first gate electrode is located in a NMOS region, and said low work function nitrided metal alloy of said first gate electrode is coupled to a gate dielectric.  
   
   
       11 . A CMOS circuit comprising: 
 a first gate electrode having a high work function nitrided metal alloy and a low work function nitrided metal alloy; and    a second gate electrode having a low work function nitrided metal alloy.    
   
   
       12 . The CMOS circuit of  claim 11  wherein said high work function nitrided metal alloy has a majority atomic concentration of Ru.  
   
   
       13 . The CMOS circuit of  claim 11  wherein said low work function nitrided metal alloy has a majority atomic concentration of Ta.  
   
   
       14 . The CMOS circuit of  claim 11  wherein said high work function nitrided metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       15 . The CMOS circuit of  claim 11  wherein said low work function nitrided metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       16 . The CMOS circuit of  claim 11  wherein a work function of said first gate electrode is controlled by the amount of said high work function nitrided metal alloy and said low work function nitrided metal alloy.  
   
   
       17 . The CMOS circuit of  claim 11  wherein a work function of said second gate electrode is controlled by the amount of said low work function nitrided metal alloy.  
   
   
       18 . The CMOS circuit of  claim 11  wherein said first gate electrode and said second gate electrode have a thickness between 5 Å and 2500 Å.  
   
   
       19 . The CMOS circuit of  claim 1   1  wherein a thickness of said high work function nitrided metal alloy is different from a thickness of said low work function nitrided metal alloy.  
   
   
       20 . The CMOS circuit of  claim 11  wherein said first gate electrode is located in a PMOS region, and said high work function nitrided metal alloy of said first gate electrode is coupled to a gate dielectric.  
   
   
       21 . A method of manufacturing a semiconductor wafer comprising: 
 providing a semiconductor substrate;    forming a layer of gate oxide over said semiconductor substrate;    forming a layer of high work function nitrided metal alloy over said semiconductor substrate;    patterning said layer of high work function nitrided metal alloy;    etching said layer of high work function nitrided metal alloy;    forming a layer of low work function nitrided metal alloy over said semiconductor substrate; and    forming gate electrodes by patterning and etching said layer of low work function nitrided metal alloy and said layer of high work function nitrided metal alloy.    
   
   
       22 . The method of  claim 21  wherein said layer of high work function nitrided metal alloy has a majority atomic concentration of Ru.  
   
   
       23 . The method of  claim 21  wherein said layer of low work function nitrided metal alloy has a majority atomic concentration of Ta.  
   
   
       24 . The method of  claim 21  wherein said layer of high work function nitrided metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       25 . The method of  claim 21  wherein said layer of low work function nitrided metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       26 . The method of  claim 21  wherein said gate electrodes have a thickness between 5 Å and 2500 Å.  
   
   
       27 . The method of  claim 21  wherein a thickness of said layer of high work function nitrided metal alloy is different from a thickness of said layer of low work function nitrided metal alloy.  
   
   
       28 . The method of  claim 21  wherein said steps of forming a layer of high work function nitrided metal alloy and a layer of low work function nitrided metal alloy includes reactive sputtering of said layer of high work function nitrided metal alloy and said layer of low work function nitrided metal alloy.  
   
   
       29 . The method of  claim 21  further comprising the step of forming a layer of metal cladding prior to said step of forming gate electrodes.  
   
   
       30 . A method of manufacturing a semiconductor wafer comprising: 
 providing a semiconductor substrate;    forming a layer of gate oxide over said semiconductor substrate;    forming a layer of low work function nitrided metal alloy over said semiconductor substrate;    patterning said layer of low work function nitrided metal alloy;    etching said layer of low work function nitrided metal alloy;    forming a layer of high work function nitrided metal alloy over said semiconductor substrate; and    forming gate electrodes by patterning and etching said layer of high work function nitrided metal alloy and said layer of low work function nitrided metal alloy.    
   
   
       31 . The method of  claim 30  wherein said layer of high work function nitrided metal alloy has a majority atomic concentration of Ru.  
   
   
       32 . The method of  claim 30  wherein said layer of low work function nitrided metal alloy has a majority atomic concentration of Ta.  
   
   
       33 . The method of  claim 30  wherein said layer of high work function nitrided metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       34 . The method of  claim 30  wherein said layer of low work function nitrided metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       35 . The method of  claim 30  wherein said gate electrodes have a thickness between 5 Å and 2500 Å.  
   
   
       36 . The method of  claim 30  wherein a thickness of said layer of high work function nitrided metal alloy is different from a thickness of said layer of low work function nitrided metal alloy.  
   
   
       37 . The method of  claim 30  wherein said steps of forming a layer of high work function nitrided metal alloy and a layer of low work function nitrided metal alloy includes reactive sputtering of said layer of high work function nitrided metal alloy and said layer of low work function nitrided metal alloy.  
   
   
       38 . The method of  claim 30  further comprising the step of forming a layer of metal cladding prior to said step of forming gate electrodes.  
   
   
       39 . A method of manufacturing a semiconductor wafer comprising: 
 providing a semiconductor substrate;    forming a layer of gate oxide over said semiconductor substrate;    forming a layer of high work function metal alloy over said semiconductor substrate;    patterning said layer of high work function metal alloy;    etching said layer of high work function metal alloy;    forming a layer of low work function metal alloy over said semiconductor substrate;    forming gate electrodes by patterning and etching said layer of low work function metal alloy and said layer of high work function metal alloy; and    nitriding said gate electrodes.    
   
   
       40 . The method of  claim 39  wherein said step of nitriding includes nitrogen ion implantation, plasma nitridation, or ammonia anneal.  
   
   
       41 . The method of  claim 39  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru.  
   
   
       42 . The method of  claim 39  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta.  
   
   
       43 . The method of  claim 39  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       44 . The method of  claim 39  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       45 . The method of  claim 39  wherein said gate electrodes have a thickness between 5 Å and 2500 Å.  
   
   
       46 . The method of  claim 39  wherein a thickness of said layer of high work function metal alloy is different from a thickness of said layer of low work function metal alloy.  
   
   
       47 . The method of  claim 39  further comprising the step of forming a layer of metal cladding after said nitriding step.  
   
   
       48 . A method of manufacturing a semiconductor wafer comprising: 
 providing a semiconductor substrate;    forming a layer of gate oxide over said semiconductor substrate;    forming a layer of high work function metal alloy over said semiconductor substrate;    nitriding said layer of high work function metal alloy;    patterning said layer of high work function metal alloy;    etching said layer of high work function metal alloy;    forming a layer of low work function metal alloy over said semiconductor substrate;    nitriding said layer of low work function metal alloy; and    forming gate electrodes by patterning and etching said layer of low work function nitrided metal alloy and said layer of high work function nitrided metal alloy.    
   
   
       49 . The method of  claim 48  wherein said steps of nitriding includes nitrogen ion implantation, plasma nitridation, or ammonia anneal.  
   
   
       50 . The method of  claim 48  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru.  
   
   
       51 . The method of  claim 48  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta.  
   
   
       52 . The method of  claim 48  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       53 . The method of  claim 48  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       54 . The method of  claim 48  wherein said gate electrodes have a thickness between 5 Å and 2500 Å.  
   
   
       55 . The method of  claim 48  wherein a thickness of said layer of high work function nitrided metal alloy is different from a thickness of said layer of low work function nitrided metal alloy.  
   
   
       56 . A method of manufacturing a semiconductor wafer comprising: 
 providing a semiconductor substrate;    forming a layer of gate oxide over said semiconductor substrate;    forming a layer of low work function metal alloy over said semiconductor substrate;    patterning said layer of low work function metal alloy;    etching said layer of low work function metal alloy;    forming a layer of high work function metal alloy over said semiconductor substrate;    forming gate electrodes by patterning and etching said layer of high work function metal alloy and said layer of low work function metal alloy; and    nitriding said gate electrodes.    
   
   
       57 . The method of  claim 56  wherein said step of nitriding includes nitrogen ion implantation, plasma nitridation, or ammonia anneal.  
   
   
       58 . The method of  claim 56  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru.  
   
   
       59 . The method of  claim 56  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta.  
   
   
       60 . The method of  claim 56  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       61 . The method of  claim 56  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       62 . The method of  claim 56  wherein said gate electrodes have a thickness between 5 Å and 2500 Å.  
   
   
       63 . The method of  claim 56  wherein a thickness of said layer of high work function metal alloy is different from a thickness of said layer of low work function metal alloy.  
   
   
       64 . The method of  claim 56  further comprising the step of forming a layer of metal cladding after said nitriding step.  
   
   
       65 . A method of manufacturing a semiconductor wafer comprising: 
 providing a semiconductor substrate;    forming a layer of gate oxide over said semiconductor substrate;    forming a layer of low work function metal alloy over said semiconductor substrate;    nitriding said layer of low work function metal alloy;    patterning said layer of low work function metal alloy;    etching said layer of low work function metal alloy;    forming a layer of high work function metal alloy over said semiconductor substrate;    nitriding said layer of high work function metal alloy; and    forming gate electrodes by patterning and etching said layer of high work function metal alloy and said layer of low work function metal alloy.    
   
   
       66 . The method of  claim 65  wherein said step of nitriding includes nitrogen ion implantation, plasma nitridation, or ammonia anneal.  
   
   
       67 . The method of  claim 65  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru.  
   
   
       68 . The method of  claim 65  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta.  
   
   
       69 . The method of  claim 65  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       70 . The method of  claim 65  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       71 . The method of  claim 65  wherein said gate electrodes have a thickness between 5 Å and 2500 Å.  
   
   
       72 . The method of  claim 65  wherein a thickness of said layer of high work function metal alloy is different from a thickness of said layer of low work function metal alloy.  
   
   
       73 . A method of manufacturing a semiconductor wafer comprising: 
 providing a semiconductor substrate;    forming a layer of gate oxide over said semiconductor substrate;    forming a layer of high work function metal alloy over said semiconductor substrate;    forming layer of low work function metal over said semiconductor substrate;    patterning said layer of low work function metal;    etching said layer of low work function metal;    annealing said semiconductor substrate, said annealing step forming regions of interdiffused metal alloy where said layer of low work function metal interdiffused with said layer of high work function metal alloy;    nitriding said high work function metal alloy and said interdiffused metal alloy; and    forming gate electrodes by patterning and etching said semiconductor substrate.    
   
   
       74 . The method of  claim 73  wherein said steps of nitriding include nitrogen ion implantation, plasma nitridation, or ammonia anneal.  
   
   
       75 . The method of  claim 73  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru.  
   
   
       76 . The method of  claim 73  wherein said layer of low work function metal is Ta.  
   
   
       77 . The method of  claim 73  wherein said layer of high work function metal alloy has a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       78 . The method of  claim 73  wherein said layer of low work function metal is Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       79 . The method of  claim 73  wherein said layer of low work function metal is a metal alloy having a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.  
   
   
       80 . A method of manufacturing a semiconductor wafer comprising: 
 providing a semiconductor substrate;    forming a layer of gate oxide over said semiconductor substrate;    forming a layer of low work function metal alloy over said semiconductor substrate;    forming a layer of high work function metal over said semiconductor substrate;    nitriding said layer of high work function metal;    patterning said layer of high work function metal;    etching said layer of high work function metal alloy;    annealing said semiconductor substrate, said annealing step forming regions of interdiffused metal alloy where said layer of high work function metal interdiffused with said layer of low work function metal alloy;    nitriding said low work function metal alloy and said interdiffused metal alloy; and    forming gate electrodes by patterning and etching said semiconductor substrate.    
   
   
       81 . The method of  claim 80  wherein said step of nitriding includes nitrogen ion implantation, plasma nitridation, or ammonia anneal.  
   
   
       82 . The method of  claim 80  wherein said layer of high work function metal is Ru.  
   
   
       83 . The method of  claim 80  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta.  
   
   
       84 . The method of  claim 80  wherein said layer of high work function metal is Ru, Pt, Pd, Ir, or Rh.  
   
   
       85 . The method of  claim 80  wherein said layer of high work function metal is a metal alloy having a majority atomic concentration of Ru, Pt, Pd, Ir, or Rh.  
   
   
       86 . The method of  claim 80  wherein said layer of low work function metal alloy has a majority atomic concentration of Ta, Ti, Hf, Mo, W, Cr, or Zr.