System and method for arbitration of a plurality of processing modules

Abstract

Method and apparatus for an arbitrated high speed control data bus system providing high speed communications between microprocessor modules in a complex digital processing environment. The system features a simplified hardware architecture featuring fast FIFO queuing, TTL CMOS compatible level clocking signals, single bus master arbitration, synchronous clocking, DMA, and unique module addressing for multiprocessor systems. The system includes a parallel data bus with sharing bus masters residing on each processing module decreeing the communication and data transfer protocol. Bur arbitration is performed over a dedicated, independent, serial arbitration line. Each requesting module competes for access to the parallel data bus by placing the address of the requesting module on the arbitration line and monitoring the arbitration line for collisions, eliminating the need for both bus request and bus grant signals.

1 . A method for controlling access to a data bus which is shared by a plurality of data processing modules, the method comprising: 
 providing an arbitration bus independent from the data bus;    placing a unique address of the data processing module bit by bit on the arbitration bus, while monitoring the arbitration bus simultaneously, wherein the data processing module stops placing its address when a bit different from its own address bit is detected on the arbitration bus;    asserting the data bus when the data processing module succeeds to place and detect all the bits of its own address on the arbitration bus; and    withholding the arbitration bus until data transfer is completed.    
   
   
       2 . The method of  claim 1  further comprising a step of monitoring the arbitration bus for a predetermined duration before placing the address on the arbitration bus, whereby the data processing module places its own address only if the arbitration bus is not busy.  
   
   
       3 . The method of  claim 2  wherein the data processing module monitors the arbitration bus for a period equal to the length of the address of the data processing module.  
   
   
       4 . The method of  claim 1  wherein the address of the plurality of data processing modules are prioritized.  
   
   
       5 . The method of  claim 1  wherein the address of the data processing module is a binary code.  
   
   
       6 . An apparatus for transferring data through a data bus, the apparatus comprising: 
 a data bus;    an arbitration bus; and    a plurality of data processing modules, each data processing module comprising a bus controller for placing a unique address of the data processing module in series on the arbitration bus while detecting occurrence of collision on the arbitration bus simultaneously, whereby the data processing module withholds the data bus if the data processing module succeeds to place all the bits of its own address on the arbitration bus without collision.    
   
   
       7 . The apparatus of  claim 6  wherein the bus controller of the data processing module monitors the arbitration bus for a predetermined duration before placing the address on the arbitration bus, whereby the data processing module places its own address only if the arbitration bus is not busy.  
   
   
       8 . The apparatus of  claim 7  wherein the data processing module monitors the arbitration bus for a period equal to the length of the address of the data processing module.  
   
   
       9 . The apparatus of  claim 6  wherein the address of the plurality of data processing modules are prioritized.  
   
   
       10 . The apparatus of  claim 6  wherein the address of the data processing module is a binary code.