System and method to reduce noise in a substrate

Abstract

Disclosed herein is a system adapted to reduce noise in a substrate of a chip. The chip may include a substrate having a first well disposed there atop. The first well may be a deep well. A second well and a third may also be disposed within the first well. A first transistor may be disposed in the second well. A quiet voltage source may be connected to a body of the first transistor. A second transistor may be disposed in the third well. The first transistor may be a PMOS transistor and the second transistor may be an NMOS transistor. A noisy voltage source may be coupled to a source of the first transistor. A body of the first transistor may be resistively coupled to the second well.

1 . A method for reducing noise in an electronic device, the method comprising: 
 shielding a substrate layer from a circuit layer employing a shielding layer;    coupling a first circuit to the shielding layer,    coupling a second circuit to the shielding layer; and    coupling the shielding layer to the substrate layer, wherein coupling the shielding layer to the substrate layer reduces noise transfer in the electronic device.    
   
   
       2 . The method according to  claim 1 , wherein shielding the substrate layer from the circuit layer comprises disposing the shielding layer between the substrate layer and the circuit layer.  
   
   
       3 . The method according to  claim 1 , wherein shielding the substrate layer from the circuit layer comprises disposing a deep N-well between the substrate layer and the circuit layer.  
   
   
       4 . The method according to  claim 1 , further comprising coupling one of a quiet voltage source and a noisy voltage source to the first circuit.  
   
   
       5 . The method according to  claim 1 , further comprising coupling one of a quiet voltage source and a noisy voltage source to the second circuit.  
   
   
       6 . The method according to  claim 1 , wherein coupling the first circuit to the shielding layer comprises capacitively coupling the first circuit to the shielding layer.  
   
   
       7 . The method according to  claim 1 , wherein coupling the second circuit to the shielding layer comprises resistively coupling the second circuit to the shielding layer.  
   
   
       8 . The method according to  claim 1 , further comprising: 
 coupling a noisy voltage source to the second circuit; and    coupling a quiet voltage source to the first circuit.    
   
   
       9 . The method according to  claim 8 , further comprising producing approximately equal voltage levels from the noisy voltage source and the quiet voltage source.  
   
   
       10 . The method according to  claim 1 , further comprising: 
 coupling a quiet voltage source to the second circuit; and    coupling a noisy voltage source to the first circuit.    
   
   
       11 . The method according to  claim 10 , further comprising producing approximately equal voltage levels from the noisy voltage source and the quiet voltage source.  
   
   
       12 . The method according to  claim 1 , wherein the first circuit comprises a first transistor.  
   
   
       13 . The method according to  claim 12 , wherein the first transistor comprises a p-type transistor.  
   
   
       14 . The method according to  claim 13 , further comprising coupling a voltage source to a source of the p-type transistor, wherein the p-type transistor comprises an p-channel metal oxide semiconductor (PMOS) transistor.  
   
   
       15 . The method according to  claim 13 , further comprising coupling a voltage source to a body of the p-type transistor, wherein the p-type transistor comprises an p-channel metal oxide semiconductor (PMOS) transistor.  
   
   
       16 . The method according to  claim 1 , wherein the second circuit comprises a second transistor.  
   
   
       17 . The method according to  claim 16 , wherein the second transistor comprises an n-type transistor.  
   
   
       18 . The method according to  claim 17 , further comprising coupling a voltage source to a source of the n-type transistor, wherein the n-type transistor comprises an n-channel metal oxide semiconductor (NMOS) transistor.  
   
   
       19 . The method according to  claim 17 , further comprising coupling a voltage source to a body of the n-type transistor, wherein the n-type transistor comprises an n-channel metal oxide semiconductor (NMOS) transistor.  
   
   
       20 . The method according to  claim 1 , wherein coupling the shielding layer to the substrate layer comprises capacitively coupling the shielding layer to the substrate layer.