Reducing dopant losses during annealing processes

Abstract

A method of reducing dopant losses is provided. The method includes providing a transistor structure having a first region, implanting a dopant into the first region, depositing a control layer adjacent the first region, and performing a first annealing process on the transistor structure. The control layer is operable to prevent at least a portion of the dopant in the first region from diffusing out of the first region toward the control layer during the first annealing process.

1 - 14 . (canceled)  
   
   
       15 . An integrated circuit, comprising: 
 a transistor comprising a first active region, the first active region having been formed at least by: 
 implanting a dopant into a first region of a transistor structure;  
 forming a control layer adjacent the first region, the control layer operable to prevent at least a portion of the dopant in the first region from diffusing from the first region toward the control layer during annealing; and  
 performing a first annealing process on the transistor structure.  
   
   
   
       16 . The integrated circuit of  claim 15 , wherein: 
 the first active region is an active source region;    the transistor further comprises an active drain region;    the active drain region having been formed at least by: 
 implanting a dopant into a second region of the transistor structure;  
 forming the control layer adjacent the second region, the control layer operable to prevent at least a portion of the dopant in the second region from diffusing from the second region toward the control layer during annealing; and  
 performing the first annealing process on the transistor structure.  
   
   
   
       17 . The integrated circuit of  claim 16 , wherein: 
 the transistor further comprises an active gate region;    the active gate region having been formed at least by: 
 implanting a dopant into a third region of the transistor structure;  
 forming the control layer adjacent the third region, the control layer operable to prevent at least a portion of the dopant in the third region from diffusing from the third region toward the control layer during annealing; and  
 performing the first annealing process on the transistor structure.  
   
   
   
       18 . The integrated circuit of  claim 15 , wherein the control layer comprises an oxide layer.  
   
   
       19 . The integrated circuit of  claim 15 , wherein the control layer has a thickness of at least 50 angstroms.  
   
   
       20 . The integrated circuit of  claim 15 , wherein the control layer is formed over a thin oxide layer adjacent the first region.  
   
   
       21 . The integrated circuit of  claim 15 , the first active region of the transistor 
 having been formed at least by:    removing a first portion of the control layer such that a second first portion of the control layer adjacent a first portion of a first surface of the doped first region remains; and    depositing a metal layer adjacent the doped first region and the remaining second portion of the control layer such that the remaining second portion of the control layer prevents the metal layer from contacting the first portion of the first surface the doped first region.    
   
   
       22 . The integrated circuit of  claim 21 , wherein the first region of the transistor comprises a gate poly region.  
   
   
       23 . The integrated circuit of  claim 22 , wherein the first surface of the doped first region is a side surface of the gate poly region.  
   
   
       24 . The integrated circuit of  claim 21 , the first active region of the transistor having been formed at least by performing a second annealing process on the transistor structure.