Computer system and method for executing interrupt instructions in operating modes

Abstract

A computer system is disclosed herein including a given microprocessor specifically designed to operate in a virtual operating mode that allows a software program previously written for an earlier designed single program microprocessor to execute in a protected, paged, multi-tasking environment under a particularly designed host operating software program. The system also includes means for executing software interrupt (INTn) instructions, using emulation software forming part of the host program in order to emulate the way in which these instructions would have been executed by the earlier microprocessor. As a unique improvement to this overall computer system, certain ones of the INTn instructions are executed by means of emulation software while others are executed by means of the previously written program in cooperation with the given microprocessor and its host operating software program.

1 - 4 . (canceled)  
     
     
         5 . A microprocessor comprising: 
 means for executing instructions including a software interrupt instruction; and    means for accessing a bit in a bitmap structure in response to said software interrupt instruction, said means for executing instructions to execute an interrupt emulation routine in response to said software interrupt instruction if said bit is in a first state and to execute a non-emulating interrupt handling routine in response to said software interrupt instruction if said bit is in a second state.    
     
     
         6 . The microprocessor of  claim 5  further comprising a software interrupt register, wherein said microprocessor is capable of determining an execution address based on a value of an operand to said software interrupt instruction which is stored in said software interrupt register.  
     
     
         7 . The microprocessor of  claim 5  wherein said microprocessor is capable of determining an execution address based on a value of an operand to said software interrupt instruction.  
     
     
         8 . The microprocessor of  claim 5  wherein said bitmap structure is associated with a task and wherein an operand of said software interrupt instruction indexes into said bitmap structure to designate handling of said software interrupt instruction.  
     
     
         9 . A microprocessor comprising: 
 execution means for executing a software interrupt instruction having an operand (n) to designate one of a plurality of interrupts; and    means for causing certain ones of said plurality of interrupts to be handled by means of software emulation while allowing certain others of the plurality of interrupts to be executed by means of a previously written program and not by emulation.    
     
     
         10 . The microprocessor of  claim 9  further comprising a software interrupt register, wherein said microprocessor is capable of determining an execution address based on a value of an operand to said software interrupt instruction which is stored in said software interrupt register.  
     
     
         11 . The microprocessor of  claim 9  wherein said microprocessor is also capable of determining an execution address based on said operand.  
     
     
         12 . The microprocessor of  claim 9  wherein said means for causing includes logic to access a bitmap, wherein said bitmap is associated with a task and wherein said operand of said software interrupt instruction indexes into said bitmap to designate handling of said software interrupt instruction.  
     
     
         13 . A microprocessor comprising: 
 an execution unit to execute instructions including a first software interrupt instruction, having a first operand specifying a first interrupt number; and    logic to access, in response to said first software interrupt instruction and said first interrupt number, a table including a bit corresponding to said first interrupt number, and in response to said bit being in a first state to execute an emulation routine and in response to said bit being in a second state to execute a non-emulating interrupt handling routine.    
     
     
         14 . The microprocessor of  claim 13  further comprising a first software interrupt register, wherein said microprocessor is also capable of determining an execution address based on said first interrupt number which is stored in said first software interrupt register.  
     
     
         15 . The microprocessor of  claim 13  wherein said microprocessor is also capable of determining an execution address based on a value of said first operand to said first software interrupt instruction.  
     
     
         16 . The microprocessor of  claim 15  wherein said microprocessor is designed to operate in a virtual operating mode that allows previously written programs to operate in a protected, paged, multi-tasking environment.  
     
     
         17 . The microprocessor of  claim 13  wherein said microprocessor is to operate in a virtual operating mode.  
     
     
         18 . The microprocessor of  claim 17  wherein said microprocessor is to execute in a protected, paged, multi-tasking environment.  
     
     
         19 . The microprocessor of  claim 13  wherein said table comprises a series of 256 bits, one for each of a set of 256 software interrupt instructions.  
     
     
         20 . The microprocessor of  claim 13  wherein said table is associated with a specific task.  
     
     
         21 . The microprocessor of  claim 20  wherein for each of a plurality of tasks, a different associated table is to be consulted by the microprocessor, and wherein said different associated table is indexed into based on said first operand of said first software interrupt instruction.  
     
     
         22 . The microprocessor of  claim 21  wherein said first software interrupt instruction is part of a program, and wherein if said bit is a logical ‘1’, then said microprocessor is to perform execution of an interrupt routine as in an 8086 microprocessor according to the program and wherein if said bit is a logical ‘0’, then said microprocessor is to trap said first software interrupt instruction for emulation.  
     
     
         23 . The microprocessor of  claim 20  wherein a plurality of DOS programs each has an associated table.  
     
     
         24 . The microprocessor of  claim 13  wherein said table is associated with a software program.  
     
     
         25 . The microprocessor of  claim 13  wherein said first software interrupt instruction is part of a program, and wherein if said bit is a logical ‘1’, then said microprocessor is to perform execution of an interrupt routine as in an 8086 microprocessor according to the program and wherein if said bit is a logical ‘0’, then said microprocessor is to trap said first software interrupt instruction for emulation.  
     
     
         26 . The microprocessor of  claim 13  wherein said first software interrupt instruction is part of a program, and wherein if said bit is a logical ‘1’, then said microprocessor is to perform execution of an interrupt routine according to the program and wherein if said bit is a logical ‘0’, then said microprocessor is to trap said first software interrupt instruction for emulation.  
     
     
         27 . An article comprising a machine readable medium having stored thereon a plurality of instructions which, if executed by a microprocessor of a first type capable of executing a set of instructions executable on a microprocessor of a second type, cause said microprocessor of said first type to perform operations comprising: 
 an operating system, said operating system including a user programmable bit map including a series of mode bits corresponding to said set of instructions, said mode bits designating whether an instruction of said set of instructions is emulated when executed on said microprocessor of said first type, or executed on said microprocessor of said first type without emulation via said set of instructions executable on microprocessor of a second type, wherein a selection to emulate an instruction or to execute an instruction without emulation is programmable by a programmer.    
     
     
         28 . The article of  claim 27 , wherein said set of instructions includes interrupt instructions.  
     
     
         29 . The article of  claim 28 , wherein said microprocessor of said second type is an earlier designed microprocessor with respect to said microprocessor of said first type.  
     
     
         30 . The article of  claim 29 , further including an emulator for emulating execution of said set of instructions when executed on said microprocessor of said first type, as said instructions would be executed on said microprocessor of said second type.  
     
     
         31 . The article of  claim 30 , wherein said operating system is capable of performing multitasking operations.  
     
     
         32 . The article of  claim 31 , wherein said microprocessor of said first type is capable of executing in a virtual mode including a protected, paged, and multitasking environment, and wherein said microprocessor of said second type is unable to execute in said virtual mode.