Processor using less hardware and instruction conversion apparatus reducing the number of types of instructions

Abstract

A processor which decodes and executes an instruction sequence includes: a state hold unit for holding, when a predetermined instruction is executed, a renewal state for an execution result of the predetermined instruction; an obtaining unit for obtaining an instruction sequence composed of instructions matching instructions assigned to an instruction set of the processor, where the instruction set is assigned first conditional instructions, a first state condition for a first conditional instruction being mutually exclusive with a second state condition for a second conditional instruction which has a same operation code as the first conditional instruction, the instruction set not being assigned the second conditional instruction, and the first state condition and the second state condition specifying either of one state and a plurality of states; a decoding unit for decoding each instruction in the obtained instruction sequence one by one; a judging unit for judging whether the renewal state is included in either of the state and the plurality of states specified by the first state condition in the first conditional instruction, when the decoding unit decodes the first conditional instruction; and an execution unit for executing, only if a judgement result by the judging unit is affirmative, an operation specified by the operation code in the first conditional instruction decoded by the decoding unit.

1 - 28 . (canceled)  
   
   
       29 . A processor for executing an instruction sequence generated by converting a program that is capable of being described by mutually exclusive first and second conditional instructions, so that the instruction sequence includes only the first conditional instruction out of the first and second conditional instructions, 
 wherein the processor has only the first conditional instruction out of the first and second conditional instructions.    
   
   
       30 . The processor of  claim 29 , 
 wherein the first conditional instruction is a conditional transfer instruction.    
   
   
       31 . The processor of  claim 29 , 
 wherein the first conditional instruction is a conditional arithmetic instruction.    
   
   
       32 . A processor for executing an instruction sequence generated by converting a program that is capable of being described by mutually exclusive first and second conditional instructions, so that the instruction sequence includes only the first conditional instruction out of the first and second conditional instructions, 
 wherein the processor is operable to decode only the first conditional instruction out of the first and second conditional instructions.    
   
   
       33 . The processor of  claim 32 , 
 wherein the first conditional instruction is a conditional transfer instruction.    
   
   
       34 . The processor of  claim 32 , 
 wherein the first conditional instruction is a conditional arithmetic instruction.    
   
   
       35 . A processor for executing an instruction sequence generated by converting a program that is capable of being described by mutually exclusive first and second conditional instructions, so that the instruction sequence includes only the first conditional instruction out of the first and second conditional instructions, 
 wherein the processor is operable to execute only the first conditional instruction out of the first and second conditional instructions.    
   
   
       36 . The processor of  claim 35 , 
 wherein the first conditional instruction is a conditional transfer instruction.    
   
   
       37 . The processor of  claim 35 , 
 wherein the first conditional instruction is a conditional arithmetic instruction.    
   
   
       38 . A processor that executes an instruction sequence, comprising: 
 a decoding unit operable to decode an instruction sequence generated by converting a program that is capable of being described by mutually exclusive first and second conditionally instructions, so that the instruction sequence includes only the first conditional instruction out of the first and second conditional instructions; and    an executing unit operable to execute the instruction sequence decoded by the decoding unit;    wherein the decoding unit is operable to decode only the first conditional instruction out of the first and second conditional instructions.    
   
   
       39 . An instruction conversion apparatus for converting a program that is capable of being described by mutually exclusive first and second conditional instructions into an instruction sequence executable by a processor, 
 wherein the instruction conversion apparatus, when only the first conditional instruction out of the first and second conditional instructions is decodable by the processor, interchanges (a) a condition of the second conditional instruction with a condition of the first conditional instruction, and (b) an instruction executed when the condition of the second conditional instruction is satisfied with an instruction executed when the condition of the second conditional instruction is not satisfied.    
   
   
       40 . An instruction conversion apparatus, comprising: 
 an intermediate code generating unit operable to generate an intermediate code sequence by converting a program that is capable of being described by mutually exclusive first and second conditional instructions;    a detecting unit operable to detect, from the intermediate code sequence, (a) a conditional instruction that judges whether to execute one of a first operation and a second operation, (b) a first operation code that executes an instruction when the judgment result of the conditional instruction is to execute the first operation, and (c) a second operation code that executes an instruction when the judgment result of the conditional instruction is to execute the second operation; and    an interchanging unit operable, when only the first conditional instruction out of the first and second conditional instruction is decodable by a processor, to interchange (a) the second conditional instruction with the first conditional instruction, and (b) an operation of the first operation with an operation of the second operation.