Low power flash memory cell and method

Abstract

Flash memory cells are provided with a high-k material interposed between a floating polysilicon gate and a control gate. A tunnel oxide is interposed between the floating polysilicon gate and a substrate. Methods of forming flash memory cells are also provided comprising forming a first polysilicon layer over a substrate. Forming a trench through the first polysilicon layer and into the substrate, and filling the trench with an oxide layer. Depositing a second polysilicon layer over the oxide, such that the bottom of the second polysilicon layer within the trench is above the bottom of the first polysilicon layer, and the top of the second polysilicon layer within the trench is below the top of the first polysilicon layer. The resulting structure may then be planarized using a CMP process. A high-k dielectric layer may then be deposited over the first polysilicon layer. A third polysilicon layer may then be deposited over the high-k dielectric layer and patterned using photoresist to form a flash memory gate structure. During patterning, exposed second polysilicon layer is etched. An etch stop is detected at the completion of removal of the second polysilicon layer. A thin layer of the first polysilicon layer remains, to be carefully removed using a subsequent selective etch process. The high-k dielectric layer may be patterned to allow for formation of non-memory transistors in conjunction with the process of forming the flash memory cells.

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       9 . A flash memory cell structure comprising a tunnel oxide overlying a substrate, a floating polysilicon gate overlying the tunnel oxide, a high-k dielectric layer overlying the floating polysilicon gate, and a control gate overlying the high-k dielectric layer.  
   
   
       10 . The flash memory cell structure of  claim 9 , wherein the high-k dielectric layer is hafnium oxide or zirconium oxide.  
   
   
       11 . The flash memory cell structure of  claim 9 , further comprising a source region and a drain region separated from each other by the gate stack comprising the tunnel oxide, the floating polysilicon gate, the high-k dielectric layer and the control gate.  
   
   
       12 . The flash memory cell structure of  claim 9 , further comprising non-memory transistors formed on the substrate.  
   
   
       13 . The flash memory cell structure of  claim 9 , wherein the control gate has a silicide upper surface formed by a salicide process.  
   
   
       14 . The flash memory cell strcuture of  claim 9 , wherein the control gate is doped polysilicon.  
   
   
       15 . The flash memory cell structure of  claim 9 , wherein the control gate is n +  doped polysilicon.  
   
   
       16 . The flash memory cell structure of  claim 9 , wherein the control gate is p +  doped polysilicon.