Semiconductor integrated circuit

Abstract

A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

1 - 25 . (canceled)  
   
   
       26 . A semiconductor integrated circuit comprising: 
 a first global data line pair including a first global data line and a second global data line;    a first sense amplifier coupled between the first global data line and the second global data line;    a plurality of first memory blocks each including a first data line, a plurality of first memory cells coupled to the first data line, and a first switch coupled between the first data line and the first global data line; and    a plurality of second memory blocks each including a second data line, a plurality of second memory cells coupled to the second data line, and a second switch coupled between the second data line and the second global data line,    wherein when information is read out from one of the plurality of first memory cells, a read signal appears on the first global data line via the first switch and the sense amplifier amplifies the read signal on the first global data line,    wherein when information is read out from one of the plurality of second memory cells, a read signal appears on the second global data line via the second switch and the sense amplifier amplifies the read signal on the second global data line, and    wherein the number of the first switches is the same as the number of the second switches.    
   
   
       27 . A semiconductor integrated circuit according to  claim 26 , 
 wherein the first global data line is directly connected to the plurality of second memory cells, and the second global data line is directly connected to the plurality of first memory cells,    wherein when information is written into one of the plurality of first memory cells a write signal is directly supplied from the second global data line to the one of the plurality of first memory cells, and    wherein when information is written into one of the plurality of second memory cells a write signal is directly supplied from the first global data line to the one of the plurality of second memory cells.    
   
   
       28 . A semiconductor integrated circuit according to  claim 26 , 
 wherein each of the plurality of first memory blocks further includes a third data line coupled to the plurality of first memory cells and a third switch coupled between the second global data line and the third data line,    wherein each of the plurality of second memory blocks further includes a fourth data line coupled to the plurality of second memory cells and a fourth switch coupled between the first global data line and the fourth data line,    wherein when information is written into one of the plurality of first memory cells, a write signal is supplied to the third data line via the third switch, and    wherein when information is written into one of the plurality of second memory cells, a write signal is supplied to the fourth data line via the fourth switch.    
   
   
       29 . A semiconductor integrated circuit according to  claim 26 , 
 wherein each of the first and second memory cells is a gain cell.    
   
   
       30 . A semiconductor integrated circuit according to  claim 29 , 
 wherein each of the plurality of first memory cells has a first storage transistor, a first read transistor, and a first write transistor,    wherein a source and drain of the first write transistor are coupled between a gate of the first storage transistor and the second global data line, and a sate of the first write transistor is coupled to a first word line,    wherein a source and drain of the first storage transistor and a source and drain of the first read transistor are coupled in series between the first data line and a first potential, and a gate of the first read transistor is coupled to the first word line,    wherein each of the plurality of second memory cells has a second storage transistor, a second read transistor, and a second write transistor,    wherein a source and drain of the second write transistor are coupled between a gate of the second storage transistor and the first global data line, and a gate of the second write transistor is coupled to a second word line, and    wherein a source and drain of the second storage transistor and a source and drain of the second read transistor are coupled in series between the second data line and the first potential, and a gate of the second read transistor is coupled to the second word line.    
   
   
       31 . A semiconductor integrated circuit according to  claim 29 , 
 wherein each of the plurality of first memory cells has a first storage transistor, a first read transistor, and a first write transistor,    wherein a source and drain of the first write transistor are coupled between a gate of the first storage transistor and the first global data line, and a gate of the first write transistor is coupled to a first write word line,    wherein a source and drain of the first storage transistor and a source and drain of the first read transistor are coupled in series between the first data line and a first potential, and a gate of the first read transistor is coupled to a first read word line,    wherein each of the plurality of second memory cells has a second storage transistor, a second read transistor is coupled to a first read word line,    wherein a source and drain of the second write transistor are coupled between a gate of the second storage transistor and the first global data line, and a gate of the second write transistor is coupled to a second write word line, and    wherein a source and drain of the second storage transistor and a source and drain of the second read transistor are coupled in series between the second data line and the first potential, and a gate of the second read transistor is coupled to a second read word line.    
   
   
       32 . A semiconductor integrated circuit according to  claim 29 , 
 wherein each of the plurality of first memory blocks further includes a third data line coupled to the plurality of first memory cells,    wherein each of the plurality of second memory blocks further includes a fourth data line coupled to the plurality of second memory cells,    wherein each of the plurality of first memory cells has a first storage transistor, a first read transistor, and a first write transistor,    wherein a source and drain of the first write transistor are coupled between a gate of the first storage transistor and the third data line, and a gate of the first write transistor is coupled to a first word line,    wherein a source and drain of the first storage transistor and a source and drain of the first read transistor are coupled in series between the first data line and a first potential, and a gate of the first read transistor is coupled to the first word line,    wherein each of the plurality of second memory cells has a second storage transistor, a second read transistor, and a second write transistor,    wherein a source and drain of the second write transistor are coupled between a gate of the second storage transistor and the fourth data line, and a gate of the second write transistor is coupled to a second word line, and    wherein a source and drain of the second storage transistor and a source and drain of the second read transistor are coupled in series between the second data line and the first potential, and a gate of the second read transistor is coupled to the second word line.    
   
   
       33 . A semiconductor integrated circuit according to  claim 29 , 
 wherein each of the plurality of first memory blocks further includes a third data line coupled to the plurality of first memory cells,    wherein each of the plurality of second memory blocks further includes a fourth data line coupled to the plurality of second memory cells,    wherein each of the plurality of first memory cells has a first storage transistor, a first read translator, and a first write transistor,    wherein a source and drain of the first write transistor are coupled between a gate of the first storage transistor and the third data line, and a gate of the first write transistor is coupled to a first write word line,    wherein a source and drain of the first storage transistor and a source and drain of the first read transistor are coupled in series between the first data line and a first potential, and a gate of the first read transistor is coupled to a first read word line,    wherein each of the plurality of second memory cells has a second storage transistor, a second read transistor, and a second write transistor,    wherein a source and drain of the second write transistor are coupled between a gate of the second storage transistor and the fourth data line, and a gate of the second write transistor is coupled to a second write word line, and    wherein a source and drain of the second storage transistor and a source and drain of the second read transistor are coupled in series between the second data line and the first potential, and a gate of the second read transistor is coupled to a second read word line.    
   
   
       34 . A semiconductor integrated circuit according to  claim 26 , 
 wherein the first global data line crosses the second global data line.    
   
   
       35 . A semiconductor integrated circuit according to  claim 34 , further comprising: 
 a second global data line pair including a third global data line and a fourth global data line;    a second sense amplifier coupled between the third global data line and the fourth global data line;    a plurality of third memory blocks each including a third data line, a plurality of third memory cells coupled to the third data line, and a third switch coupled between the third data line and the third global data line; and    a plurality of fourth memory blocks each including a fourth data line, a plurality of fourth memory cells coupled to the fourth data line, and a fourth switch coupled between the fourth data line and the fourth global data line,    wherein the number of the third switches is the same as the number of the fourth switches;    wherein the third global data line crosses the fourth global data line, and    wherein a number of cross-points of the first and second global data lines is larger than a number of cross-points of the third and fourth global data lines.