Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor

Abstract

Circuit arrangement having a load transistor and a voltage limiting circuit and method for driving a load transistor The present invention relates to a circuit arrangement having the following features: a load transistor (T) having a control connection (G) and a first and second load connection (D, S), a drive connection (IN) coupled to the control connection (G) of the load transistor (T) and serving for the application of a drive signal (Sin), a voltage limiting circuit ( 10 ) connected between one (D) of the load connections and the drive connection (G) of the transistor, a deactivation circuit ( 20 ) connected to the voltage limiting circuit ( 10 ) and serving for the deactivation of the voltage limiting circuit ( 10 ) in a manner dependent on a deactivation signal (S 22; S 23 ), which is dependent on a load current (Id) through the load transistor (T) and/or on a drive voltage (Vgs) of the load transistor (T). The invention furthermore relates to a method for driving a load transistor.

1 - 16 . (canceled)  
   
   
       17 . A circuit arrangement comprising: 
 a load transistor having a control connection and a first and second load connection;    a drive connection coupled at an input to a source of a drive signal and at an output to the control connection of the load transistor, the drive connection being configured to have the drive signal present at the output;    a voltage limiting circuit connected between one of the load connections and the. control connection of the load transistor; and    a deactivation circuit connected to the voltage limiting circuit, the deactivation circuit being configured to deactivate the voltage limiting circuit in response to a deactivation signal responsive to a operational parameter of the load transistor.    
   
   
       18 . The circuit arrangement of  claim 17 , wherein the voltage limiting circuit comprises at least one zener diode and a diode connected oppositely to the zener diode.  
   
   
       19 . The circuit arrangement of  claim 17 , wherein the deactivation circuit comprises a switch connected between one of the load connections and the control connection in series with the voltage limiting circuit.  
   
   
       20 . The circuit arrangement of  claim 17 , wherein the operational parameter comprises a load current through the load transistor falling below a predetermined value.  
   
   
       21 . The circuit arrangement of  claim 20 , wherein the deactivation circuit comprises a current measuring arrangement configured to determine a load current through the load transistor and to provide a current measurement signal and a deactivation signal generating circuit configured to compare the current measurement signal with a reference value to generate the deactivation signal.  
   
   
       22 . The circuit arrangement of  claim 21 , wherein the deactivation circuit is configured to deactivate the voltage limiting circuit after a predetermined time duration after the current measurement signal has fallen below the reference value.  
   
   
       23 . The circuit arrangement of  claim 21 , wherein the deactivation circuit is designed to deactivate the voltage limiting circuit at the earliest with the presence of a switch-off signal at the control connection.  
   
   
       24 . The circuit arrangement of  claim 21 , wherein the deactivation circuit is designed to deactivate the voltage limiting circuit at the earliest at a predetermined time duration after the presence of a switch-off signal at the control connection.  
   
   
       25 . The circuit arrangement of  claim 17 , wherein the load transistor is integrated in a first semiconductor chip and the voltage limiting circuit and the deactivation circuit are integrated in a second semiconductor chip.  
   
   
       26 . The circuit arrangement as claimed in  claim 25 , wherein the second semiconductor chip is applied to the first semiconductor chip.  
   
   
       27 . The circuit arrangement of  claim 17 , wherein the operational parameter comprises a drive voltage of the load transistor falling below a predetermined value.  
   
   
       28 . The circuit arrangement of  claim 27 , wherein the deactivation circuit comprises a voltage measuring arrangement configured to determine a drive voltage of the load transistor and to generate a voltage measurement signal and a deactivation signal generating circuit configured to compare the voltage measurement signal with a reference value to generate the deactivation signal.  
   
   
       29 . The circuit arrangement of  claim 28 , wherein the deactivation circuit is configured to deactivate the voltage limiting circuit after a predetermined time duration after the voltage measurement signal has fallen below the reference value.  
   
   
       30 . The circuit arrangement of  claim 28 , wherein the deactivation circuit is configured to deactivate the voltage limiting circuit at the earliest with the presence of a switch-off signal at the control connection.  
   
   
       31 . The circuit arrangement of  claim 28 , wherein the deactivation circuit is configured to deactivate the voltage limiting circuit at the earliest at a predetermined time duration after the presence of a switch-off signal at the control connection.  
   
   
       32 . A method for driving a load transistor having a drive connection which is coupled to a drive terminal for the application of a drive signal, and having a first and second load connection, comprising the steps of: 
 connecting a voltage limiting circuit between one of the load connections and the drive connection; and    deactivating the voltage limiting circuit in response to an operational parameter of load transistor.    
   
   
       33 . The method of  claim 32 , wherein the deactivating step is performed if a load current of the load transistor has fallen below a predetermined value.  
   
   
       34 . The method of  claim 32 , wherein the deactivating step is performed a predetermined time duration after a load current of the load transistor has fallen below a predetermined value.  
   
   
       35 . The method of  claim 33 , wherein the deactivating step is performed at the earliest with the presence of a switch-off signal at the drive terminal.  
   
   
       36 . The method of  claim 33 , wherein the deactivating step is performed at the earliest after a predetermined time duration has elapsed after the presence of a switch-off signal at the drive terminal.  
   
   
       37 . The method of  claim 35 , further comprising the step of activating the voltage limiting circuit before the presence of a switch-off signal at the drive terminal.  
   
   
       38 . The method of  claim 32 , wherein the deactivating step is performed if a drive voltage of the load transistor has fallen below a predetermined value.  
   
   
       39 . The method of  claim 32 , wherein the deactivating step is performed a predetermined time duration after a drive voltage of the load transistor has fallen below a predetermined value.  
   
   
       40 . The method of  claim 38 , wherein the deactivating step is performed at the earliest with the presence of a switch-off signal at the drive terminal.  
   
   
       41 . The method of  claim 38 , wherein the deactivating step is performed at the earliest after a predetermined time duration has elapsed after the presence of a switch-off signal at the drive terminal.  
   
   
       42 . The method of  claim 40 , further comprising the step of activating the voltage limiting circuit before the presence of a switch-off signal at the drive terminal.