US2005085002A1PendingUtilityA1

Thin film semiconductor device and its substrate sheet as well as the method for production thereof

Assignee: ADV LCD TECH DEV CT CO LTDPriority: Jul 17, 2001Filed: Oct 29, 2004Published: Apr 21, 2005
Est. expiryJul 17, 2021(expired)· nominal 20-yr term from priority
H10P 72/3408H10P 72/3406H10P 72/1918H10P 72/1914H10P 14/3411H10P 14/381H10P 14/3816H10D 86/411H10D 86/60H10D 86/0251H10D 86/0229H10D 86/0223H10D 30/6745H10D 30/6744H10D 30/6731H10D 30/0323H10D 30/0321H10D 30/0314H10D 30/67
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Claims

Abstract

A thin film semiconductor device and a method for producing it are described. In the thin film layer of semiconductor of the device, a plurality of large size single-crystalline grains of semiconductor are formed in a regulated configuration, and each of single crystalline grains is equipped with one unit of electric circuit having a gate electrode, a source electrode and drain electrode. Such regulated arrangement of large size single-crystalline grains in the semiconductor layer is realized by a process including a step of irradiating the layer of amorphous or polycrystalline semiconductor with energy beam such as excimer laser so that maximum irradiation intensity points and minimum irradiation intensity points are arranged regulatedly. The device can have a high mobility such as about 500 cm 2 /V sec.

Claims

exact text as granted — not AI-modified
1 - 29 . (canceled)  
   
   
       30 . A substrate sheet for thin film semiconductor device comprising: 
 a base layer of insulation materials,    a thin film layer of semiconductor formed on the base layer, and    a plurality of single-crystalline semiconductor grains formed in the thin film layer of semiconductor, said plurality of single-crystalline semiconductor grains being arranged in a matrix-arrayed configuration in the thin film layer of semi-conductor in a mode such that each of the single-crystalline grains adjoin to the next single-crystalline grains with being interposed by boundary areas formed in between the grains and, each of said single-crystalline semiconductor grains having the grain size of at least 2 μm.    
   
   
       31 . A substrate sheet for thin film semiconductor devices of  claim 30 , 
 wherein a control layer for heat-conduction and crystallization is formed in between the base layer and the thin film layer of semiconductor.    
   
   
       32 . A thin film semiconductor devices of claims  30  or  31 , 
 wherein a control layer for heat-conduction and crystallization is formed on the thin film layer of semiconductor.    
   
   
       33 . A thin film semiconductor device comprising: 
 a base layer of insulation materials, a thin film layer of semiconductor formed on the base layer, and    a plurality of single-crystalline semiconductor grains formed in the thin film layer of semiconductor, said plurality of single-crystalline semiconductor grains being arranged in a matrix-arrayed configuration in a mode such that each of the single-crystalline grains adjoin to the next single-crystalline grains with being interposed by boundary areas formed in between the grains, and each of said single-crystalline semiconductor grains having the grain size of at least 2 μm, and being equipped with an electric circuit having a gate electrode, a source electrode and a drain electrode.    
   
   
       34 . A thin film semiconductor device comprising: 
 a base layer of insulation materials,    a thin film layer of semiconductor formed on the base layer, and    a plurality of single-crystalline semiconductor grains formed in the thin film layer of semiconductor, said plurality of single-crystalline semiconductor grains being arranged in a matrix-arrayed configuration in a mode such that each of the single-crystalline grains adjoin to the next single-crystalline grains with being interposed by boundary areas formed in between the grains, each of said single-crystalline semiconductor grains having the grain size of at least 2 μm, and electric circuit being arranged over the plurality of single-crystalline grains in a mode of CMOS type.

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