Data interface device for accessing SDRAM

Abstract

Disclosed is a data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory). A clock and selective data capturing are used to improve an operating rate of an SDRAM interface and to match data at SDRAM data input and output times. A clock used for driving the SDRAM uses a feedback clock for synchronization in an SDRAM controller as well as the SDRAM as a clock used to drive the SDRAM. The selective data capturing uses a register part for storing data inputted into the SDRAM. The register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock.

1 . A data interface device for accessing an SDRAM (Synchronous Dynamic Random Access Memory), comprising: 
 a clock used in the SDRAM; and    selective data capturing,    wherein the clock and the selective data capturing are used to improve an operating rate of an SDRAM interface and to match data at SDRAM data input and output times.    
   
   
       2 . The data interface device of  claim 1 , wherein the clock is used to drive the SDRAM, and is a feedback clock used for synchronization in an SDRAM controller as well as the SDRAM.  
   
   
       3 . The data interface device of  claim 2 , wherein the feedback clock is generated from the SDRAM controller through a sequential path of an output pad, the SDRAM, and an input pad and is used for approximating a clock when an external SDRAM is used and an output data time point of the SDRAM.  
   
   
       4 . The data interface device of  claim 1 , wherein the selective data capturing uses a register part for storing data inputted into the SDRAM.  
   
   
       5 . The data interface device of  claim 4 , wherein the register part for storing the data is configured by double registers that are operated in an alternative manner according to a correlation between the inputted data and the feedback clock.  
   
   
       6 . The data interface device of  claim 5 , wherein an inverter is provided in an input stage of one of the registers so that phases of feedback clocks inputted into the registers can be different.  
   
   
       7 . The data interface device of  claim 5 , wherein a cycle of the feedback clock is set to two to four times that of a main clock so that an SDRAM operation can be ensured.  
   
   
       8 . The data interface device of  claim 4 , wherein the stored data is selected using a signal generated by the internal clock.  
   
   
       9 . The data interface device of  claim 4 , wherein the register part comprises: 
 a first T flip-flop for receiving a generated internal clock and outputting an internal clock selection signal;    a second T flip-flop for receiving a feedback clock in which a board clock delayed through a pad from the internal clock is fed back and outputting a feedback clock selection signal;    a first AND element for simultaneously receiving the feedback clock and an inversion signal of the feedback clock selection signal outputted from the second T flip-flop;    a second AND element for simultaneously receiving the feedback clock and the feedback clock selection signal outputted from the second T flip-flop;    a first D flip-flop for simultaneously receiving a clock outputted from the first AND element and data;    a second D flip-flop for simultaneously receiving a clock outputted from the second AND element and data;    a data selection element for selecting one of data outputted from the first D flip-flop and data outputted from the second D flip-flop in response to the internal clock selection signal outputted from the first T flip-flop; and    a third D flip-flop for simultaneously receiving the internal clock and the data outputted from the data selection element and outputting the data in response to the internal clock.    
   
   
       10 . The data interface device of  claim 9 , further comprising: 
 an inverter coupled between the first AND element and a contact point coupled to an input terminal of the second AND element and an output terminal of the second T flip-flop, the inverter generating the inversion signal of the feedback clock selection signal.    
   
   
       11 . The data interface device of  claim 9 , further comprising: 
 a third AND element for simultaneously receiving a command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the first T flip-flop; and    a fourth D flip-flop for simultaneously receiving the command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the second T flip-flop,    wherein the third AND element and the fourth D flip-flop are configured to perform reset control of the first and second T flip-flops outputting the internal clock selection signal and the feedback clock selection signal.    
   
   
       12 . The data interface device of  claim 5 , wherein the register part comprises: 
 a first T flip-flop for receiving a generated internal clock and outputting an internal clock selection signal;    a second T flip-flop for receiving a feedback clock in which a board clock delayed through a pad from the internal clock is fed back and outputting a feedback clock selection signal;    a first AND element for simultaneously receiving the feedback clock and an inversion signal of the feedback clock selection signal outputted from the second T flip-flop;    a second AND element for simultaneously receiving the feedback clock and the feedback clock selection signal outputted from the second T flip-flop;    a first D flip-flop for simultaneously receiving a clock outputted from the first AND element and data;    a second D flip-flop for simultaneously receiving a clock outputted from the second AND element and data;    a data selection element for selecting one of data outputted from the first D flip-flop and data outputted from the second D flip-flop in response to the internal clock selection signal outputted from the first T flip-flop; and    a third D flip-flop for simultaneously receiving the internal clock and the data outputted from the data selection element and outputting the data in response to the internal clock.    
   
   
       13 . The data interface device of  claim 6 , wherein the register part comprises: 
 a first T flip-flop for receiving a generated internal clock and outputting an internal clock selection signal;    a second T flip-flop for receiving a feedback clock in which a board clock delayed through a pad from the internal clock is fed back and outputting a feedback clock selection signal;    a first AND element for simultaneously receiving the feedback clock and an inversion signal of the feedback clock selection signal outputted from the second T flip-flop;    a second AND element for simultaneously receiving the feedback clock and the feedback clock selection signal outputted from the second T flip-flop;    a first D flip-flop for simultaneously receiving a clock outputted from the first AND element and data;    a second D flip-flop for simultaneously receiving a clock outputted from the second AND element and data;    a data selection element for selecting one of data outputted from the first D flip-flop and data outputted from the second D flip-flop in response to the internal clock selection signal outputted from the first T flip-flop; and    a third D flip-flop for simultaneously receiving the internal clock and the data outputted from the data selection element and outputting the data in response to the internal clock.    
   
   
       14 . The data interface device of  claim 7 , wherein the register part comprises: 
 a first T flip-flop for receiving a generated internal clock and outputting an internal clock selection signal;    a second T flip-flop for receiving a feedback clock in which a board clock delayed through a pad from the internal clock is fed back and outputting a feedback clock selection signal;    a first AND element for simultaneously receiving the feedback clock and an inversion signal of the feedback clock selection signal outputted from the second T flip-flop;    a second AND element for simultaneously receiving the feedback clock and the feedback clock selection signal outputted from the second T flip-flop;    a first D flip-flop for simultaneously receiving a clock outputted from the first AND element and data;    a second D flip-flop for simultaneously receiving a clock outputted from the second AND element and data;    a data selection element for selecting one of data outputted from the first D flip-flop and data outputted from the second D flip-flop in response to the internal clock selection signal outputted from the first T flip-flop; and    a third D flip-flop for simultaneously receiving the internal clock and the data outputted from the data selection element and outputting the data in response to the internal clock.    
   
   
       15 . The data interface device of  claim 12 , further comprising: 
 an inverter coupled between the first AND element and a contact point coupled to an input terminal of the second AND element and an output terminal of the second T flip-flop, the inverter generating the inversion signal of the feedback clock selection signal.    
   
   
       16 . The data interface device of  claim 13 , further comprising: 
 an inverter coupled between the first AND element and a contact point coupled to an input terminal of the second AND element and an output terminal of the second T flip-flop, the inverter generating the inversion signal of the feedback clock selection signal.    
   
   
       17 . The data interface device of  claim 14 , further comprising: 
 an inverter coupled between the first AND element and a contact point coupled to an input terminal of the second AND element and an output terminal of the second T flip-flop, the inverter generating the inversion signal of the feedback clock selection signal.    
   
   
       18 . The data interface device of  claim 12 , further comprising: 
 a third AND element for simultaneously receiving a command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the first T flip-flop; and    a fourth D flip-flop for simultaneously receiving the command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the second T flip-flop,    wherein the third AND element and the fourth D flip-flop are configured to perform reset control of the first and second T flip-flops outputting the internal clock selection signal and the feedback clock selection signal.    
   
   
       19 . The data interface device of  claim 13 , further comprising: 
 a third AND element for simultaneously receiving a command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the first T flip-flop; and    a fourth D flip-flop for simultaneously receiving the command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the second T flip-flop,    wherein the third AND element and the fourth D flip-flop are configured to perform reset control of the first and second T flip-flops outputting the internal clock selection signal and the feedback clock selection signal.    
   
   
       20 . The data interface device of  claim 14 , further comprising: 
 a third AND element for simultaneously receiving a command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the first T flip-flop; and    a fourth D flip-flop for simultaneously receiving the command signal and the internal clock, carrying out a logic operation and outputting a result of the operation to a reset terminal of the second T flip-flop,    wherein the third AND element and the fourth D flip-flop are configured to perform reset control of the first and second T flip-flops outputting the internal clock selection signal and the feedback clock selection signal.