Capture clock generator using master and slave delay locked loops

Abstract

A clock generator comprises a master delay locked loop (DLL) and a slave DLL to capture a data signal. The slave DLL generates a slave output signal based on a clock signal. The master DLL receives the slave output signal and compensates variations in delays of the data and clock signals to generate a capture clock signal. When the master and slave DLLs are locked, the capture clock signal is center aligned with the data signal.

1 . A memory device comprising: 
 a data receiver for receiving an input data signal to provide an internal data signal;    a receiving circuit including an input node for receiving an input clock signal, and an output node for providing an internal clock signal;    a slave delay locked loop (DLL) for receiving the internal clock signal to generate a slave signal;    a selector for selecting between the slave signal and the internal clock signal to provide a DLL input signal; and    a master DLL responsive to the DLL input signal for generating a capture signal to capture the internal signal.    
   
   
       2 . The memory device of  claim 1 , wherein the receiving circuit includes a first receiver, and a second receiver coupled in series with the first receiver between the input and output nodes.  
   
   
       3 . The memory device of  claim 2 , wherein the second receiver includes a circuit model of the data receiver.  
   
   
       4 . The memory device of  claim 3 , wherein the master DLL includes: 
 a forward path for providing the capture signal;    a feedback path for delaying a copy of the capture signal to provide a feedback signal; and    a control circuit for adjusting a timing of the capture signal based on a timing relationship between the feedback signal and the DLL input signal.    
   
   
       5 . The memory device of  claim 4 , wherein the feedback path includes a model circuit having a first circuit unit and a second circuit unit coupled in series with the first circuit unit for delaying the copy of the feedback signal, wherein the first circuit unit includes a circuit model of the second receiver of the receiving circuit, and wherein the second circuit unit includes a circuit model of the selector.  
   
   
       6 . The memory device of  claim 1 , wherein the slave DLL is configured to generate the slave signal having a 90 degrees out of phase with the internal clock signal.  
   
   
       7 . The memory device of  claim 1 , wherein the master DLL is configured to generate the capture signal having a 90 degrees out of phase with the internal data signal.  
   
   
       8 . The memory device of  claim 1 , wherein the selector is configured to select the slave signal to be the DLL input signal when the input clock signal is edge aligned with the input data signal, and wherein the selector is configured to select the internal clock signal to be the DLL input signal when the input clock signal is center aligned with the input data signal.  
   
   
       9 . A memory device comprising: 
 a data receiver for receiving an input data signal to provide an internal data signal;    a receiving circuit including an input node for receiving an input clock signal, and an output node for providing an internal clock signal, the receiving circuit also including a first receiver, and a second receiver coupled in series with the first receiver between the input and output nodes, wherein the second receiver includes a circuit model of the data receiver;    a slave delay locked loop (DLL) for receiving the internal clock signal to generate a slave signal; and    a master DLL responsive to the slave signal for generating a capture signal to capture the internal signal.    
   
   
       10 . The memory device of  claim 9 , wherein the master DLL is configured to generate the capture signal having a 90 degrees out of phase with the internal data signal.  
   
   
       11 . The memory device of  claim 9 , wherein the master DLL is configured to generate the capture signal having a 90 degrees out of phase with the internal data signal when the input clock signal is edge aligned with the input data signal.  
   
   
       12 . The memory device of  claim 9 , wherein the master DLL includes: 
 a forward path for providing the capture signal;    a feedback path for delaying a copy of the capture signal to provide a feedback signal; and    a control circuit for adjusting a timing of the capture signal based on the feedback signal.    
   
   
       13 . The memory device of  claim 12 , wherein the feedback path includes a model circuit having a first circuit unit and a second circuit unit coupled in series with the first circuit unit for delaying the copy of the feedback signal, wherein the first circuit unit includes a circuit model of the data receiver.  
   
   
       14 . A memory device comprising: 
 a receiving circuit having a receiver for receiving an input clock signal to produce an internal clock signal;    a slave delay locked loop (DLL) for receiving the internal clock signal to produce a slave signal;    a selector for selecting between the internal clock signal and the slave signal to provide a DLL input signal;    a master DLL responsive to the DLL input signal for generating a capture signal to capture an internal data signal; and    a data path circuit response to the capture signal to provide an output data signal based on the internal data signal.    
   
   
       15 . The memory device of  claim 14 , wherein the selector is configured to select the internal clock signal to be the DLL input signal when the input clock signal is center aligned with the input data signal, and wherein the selector is configured to select the slave signal to be the DLL input signal when the input clock signal is edge aligned with the input data signal.  
   
   
       16 . The memory device of  claim 14 , wherein the master DLL includes: 
 a forward path for providing the capture signal;    a feedback path for delaying a copy of the capture signal to provide a feedback signal; and    a control circuit for adjusting a timing of the capture signal based on a timing relationship between the feedback signal and the DLL input signal.    
   
   
       17 . The memory device of  claim 16 , wherein the feedback path includes model circuit having a series combination of a first circuit unit, a second circuit unit, and a third circuit unit for delaying the copy of the feedback signal, wherein the first circuit unit includes a circuit model of the receiver of the receiving circuit, wherein the second circuit unit includes a circuit model of the selector, and wherein the third circuit unit includes a circuit model of the data path circuit.  
   
   
       18 . A memory system comprising: 
 a plurality of memory cells; and    a controller coupled to the memory cells, the controller including: 
 a receiving circuit having an input node for receiving an input clock signal, and an output node for producing an internal clock signal, the receiving circuit including a first receiver, and a second receiver coupled in series with the first receiver between the input and output nodes;  
 a data receiver for receiving an input data signal from the memory cells to produce an internal data signal, wherein the second receiver of the receiving circuit includes a circuit model of the data receiver;  
 a slave delay locked loop (DLL) for receiving the internal clock signal to produce a slave signal having a 90 degrees out of phase with the internal clock signal; and  
 a master DLL responsive to the slave signal to generate a capture signal to capture the internal data signal.  
   
   
   
       19 . The memory system of  claim 18 , wherein the master DLL includes: 
 a forward path for providing the capture signal;    a feedback path for delaying a copy of the capture signal to provide a feedback signal; and    a control circuit for adjusting a timing of capture signal based on a timing relationship between the feedback signal and the DLL input signal.    
   
   
       20 . The memory system of  claim 19 , wherein the feedback path includes model circuit having a first circuit unit and a second circuit unit coupled in series with the first circuit unit for delaying the copy of the feedback signal, and wherein the first circuit unit includes a circuit model of the second receiver of the receiving circuit.  
   
   
       21 . The memory system of  claim 18 , wherein the input data signal includes a data signal representing data stored in the memory cells.  
   
   
       22 . The memory system of  claim 18 , wherein the master DLL is configured to generate the capture signal having a 90 degrees out of phase with the internal data signal.  
   
   
       23 . A memory system comprising: 
 a plurality of memory cells; and    a controller coupled to the memory cells, the controller including: 
 a receiving circuit including an input node for receiving an input clock signal, and an output node for providing an internal clock signal;  
 a data receiver for receiving an input data signal to provide an internal data signal,  
 a slave delay locked loop (DLL) for receiving the internal clock signal to generate a slave signal;  
 a multiplexer coupled to the receiving circuit and the slave DLL for providing a DLL input signal, wherein the multiplexer is configured to select the internal clock signal to be the DLL input signal when the input clock signal is center aligned with the input data signal, and wherein the multiplexer is configured to select the slave signal to be the DLL input signal when the input clock signal is edge aligned with the input data signal; and  
 a master DLL responsive to the DLL input signal for generating a capture signal to capture the internal signal.  
   
   
   
       24 . The memory system of  claim 23 , wherein the receiving circuit includes a first receiver, and a second receiver coupled in series with the first receiver between the input and output nodes.  
   
   
       25 . The memory system of  claim 24 , wherein the second receiver includes a circuit model of the data receiver.  
   
   
       26 . The memory system of  claim 25 , wherein the slave DLL is configured to generate the slave signal having a 90 degrees out of phase with the internal clock signal.  
   
   
       27 . The memory device of  claim 23 , wherein the master DLL includes: 
 a forward path for providing the capture signal;    a feedback path for delaying a copy of the capture signal to provide a feedback signal; and    a control circuit for adjusting a timing of the capture signal based on a timing relationship between the feedback signal and the DLL input signal.    
   
   
       28 . The memory system of  claim 27 , wherein the feedback path includes a model circuit having a first circuit unit and a second circuit unit coupled in series with the first circuit unit for delaying the copy of the feedback signal, wherein the first circuit unit includes a circuit model of the second receiver of the receiving circuit, and wherein the second circuit unit includes a circuit model of the multiplexer.  
   
   
       29 . A system comprising: 
 a processor;    a memory device coupled to the processor, the memory device including a plurality of memory cells to store data; and    a memory controller coupled to the memory device, the memory controller including: 
 a data receiver for receiving an input data signal to provide an internal data signal,  
 a receiving circuit including an input node for receiving an input clock signal, and an output node for providing an internal clock signal;  
 a slave delay locked loop (DLL) for receiving the internal clock signal to generate a slave signal;  
 a multiplexer for selecting between the slave signal and the internal clock signal to provide a DLL input signal; and  
 a master DLL responsive to the DLL input signal for generating a capture signal to capture the internal signal.  
   
   
   
       30 . The system of  claim 29 , wherein the receiving circuit includes a first receiver, and a second receiver coupled in series with the first receiver between the input and output nodes.  
   
   
       31 . The system of  claim 30 , wherein the second receiver includes a circuit model of the data receiver.  
   
   
       32 . The system of  claim 29 , wherein the slave DLL is configured to generate the slave signal having a 90 degrees out of phase with the internal clock signal.  
   
   
       33 . The system of  claim 29 , wherein the master DLL is configured to generate the capture signal having a 90 degrees out of phase with the internal data signal.  
   
   
       34 . The system of  claim 29 , wherein the multiplexer is configured to select the slave signal to be the DLL input signal when the input clock signal is edge aligned with the input data signal, and wherein the multiplexer is configured to select the internal clock signal to be the DLL input signal when the input clock signal is center aligned with the input data signal.  
   
   
       35 . A method comprising: 
 propagating an input data signal through a data receiver to provide an internal data signal;    propagating an input clock signal through a series combination of a first receiver and a second receiver to provide an internal clock signal, wherein the second receiver includes a circuit model of the data receiver;    generating a slave signal based on the internal clock signal; and    generating a capture signal based on the slave signal to capture the internal data signal.    
   
   
       36 . The method of  claim 35 , wherein the slave signal is 90 degrees out of phase with the internal clock signal.  
   
   
       37 . The method of  claim 36 , wherein the capture signal is 90 degrees out of phase with the internal data signal.  
   
   
       38 . The method of  claim 35 , wherein the generating the capture signal includes: 
 propagating the slave signal on a forward path;    delaying copy of capture signal to generate a feedback signal on a feedback path; and    adjusting a delay applied to the forward path based on a signal relationship between the slave signal and the feedback signal.    
   
   
       39 . The method of  claim 38 , wherein the delaying the copy of the capture signal includes propagating the copy of the capture signal through a circuit unit of the feedback path, wherein the circuit unit includes a circuit model of the receiver of the receiving circuit.  
   
   
       40 . A method comprising: 
 propagating an input data signal through a data receiver to provide an internal data signal;    propagating an input clock signal through a receiving circuit to provide an internal clock signal;    generating a slave signal based on the internal clock signal;    selecting between the internal clock signal and the slave signal to provide a delay locked loop (DLL) input signal, wherein the selecting is based on a timing relationship between the input data signal and the input clock signal; and    generating a capture signal based on the DLL input signal.    
   
   
       41 . The method of  claim 40 , wherein propagating the input clock signal includes propagating the input clock through a series combination of a first receiver and a second receiver of the receiving circuit.  
   
   
       42 . The method of  claim 41 , wherein the second receiver of the receiving circuit is a circuit model of the data receiver.  
   
   
       43 . The method of  claim 42 , wherein the DLL input signal is 90 degrees out of phase with the internal clock signal.  
   
   
       44 . The method of  claim 43 , wherein the capture signal is 90 degrees out of phase with the internal data signal.  
   
   
       45 . The method of  claim 40 , wherein the internal clock signal is selected to provide the DLL input signal when the input clock signal is center aligned with the input data signal, and wherein the slave signal is selected to provide the DLL input signal when the input clock signal is edge aligned with the input data signal.  
   
   
       46 . The method of  claim 40 , wherein the generating the capture signal includes: 
 propagating the DLL input signal on a forward path;    delaying copy of capture signal to generate a feedback signal on a feedback path; and    adjusting a delay applied to the forward path based on a signal relationship between the DLL input signal and the feedback signal.    
   
   
       47 . The method of  claim 46 , wherein the delaying the copy of the capture signal includes propagating the copy of the capture signal through a circuit unit of the feedback path, wherein the circuit unit includes a circuit model of the data receiver.