Adjustment of a clock duty cycle

Abstract

Circuits for adjusting the duty cycle of a clock(s) signal include a negative feedback loop for applying an offset signal to the uncorrected clock signal(s). The offset signal, which corresponds to a duty cycle error of the corrected clock signal(s), adjusts the slicing level of the uncorrected clock signal(s) to cause the duty cycle error to converge toward a predetermined value, for example, zero. The techniques may be used to adjust the duty cycle error of differential clock signals as well as single-ended clock signals.

1 - 18 . (canceled)  
   
   
       19 . A method comprising: 
 obtaining one or more corrected clock signals based on one or more uncorrected clock signals;    obtaining a DC offset signal corresponding to a duty cycle error of the one or more corrected clock signals; and    adjusting a slicing level for the one or more uncorrected clock signals based on the DC offset signal, wherein the adjusting includes adding the DC offset signal to the one or more uncorrected clock signals.    
   
   
       20 . The method of  claim 19  including repeating said obtaining one or more corrected clock signals, obtaining a DC offset signal and adjusting a slicing level, 
 wherein adjusting the slicing level causes the duty cycle error to converge toward a predetermined value.    
   
   
       21 . The method of  claim 20  wherein the duty cycle error converges toward zero.  
   
   
       22 . The method of  claim 21  wherein the duty cycle error is a differential duty cycle error for a pair of corrected clock signals.  
   
   
       23 . A method comprising: 
 receiving an uncorrected clock signal as an input to a negative feedback loop;    producing an integrated charge signal that is proportional to a clock duty cycle error;    producing an offset voltage signal based on the integrated charge signal; and    adjusting a slicing level for the uncorrected clock signal based on the offset voltage,    wherein the adjusting includes adding the offset voltage signal to the uncorrected clock signal.    
   
   
       24 . The method of  claim 23  wherein adjusting the slicing level includes adding the offset voltage signal to the uncorrected clock signal.  
   
   
       25 . The method of  claim 24  including: 
 amplifying a signal representing a sum of the uncorrected clock signal and the offset signal;    clamping the amplified signal; and    producing a corrected clock signal based on the clamped signal.    
   
   
       26 . The method of  claim 25  wherein the integrated charge signal is proportional to a duty cycle error of the corrected clock signal.  
   
   
       27 . The method of  claim 25  including producing a corrected clock signal having a duty cycle that converges toward a predetermined value.  
   
   
       28 . The method of  claim 25  including producing a corrected clock signal having a duty cycle that converges toward about 50%.  
   
   
       29 . The method of  claim 25  including repeatedly producing an offset voltage signal based on the integrated charge signal and adjusting a slicing level for the uncorrected clock signal based on the offset voltage.  
   
   
       30 . The method of  claim 25  wherein producing an integrated charge signal includes producing a signal indicative of a time difference between high and low states of the clock signal, 
 wherein the integrated charge signal is proportional to an integrated value of a deviation of the clock signal from a predetermined duty cycle.    
   
   
       31 . A method comprising: 
 receiving a plurality of uncorrected clock signals as input to a negative feedback loop;    producing a net integrated charge that is proportional to a duty cycle error;    producing an offset voltage signal based on the net integrated charge; and    adjusting a slicing level for the uncorrected clock signals based on the offset voltage,    wherein the adjusting includes adding the offset voltage signal to the uncorrected clock signals.    
   
   
       32 . The method of  claim 31  wherein adjusting the slicing level includes adding the offset voltage signal to the uncorrected clock signals.  
   
   
       33 . The method of  claim 32  including: 
 amplifying signals each of which represents, respectively, a sum of one of the uncorrected clock signals and the offset signal;    clamping the amplified signals; and    producing corrected clock signals based on the clamped signals.    
   
   
       34 . The method of  claim 33  wherein the net integrated charge signal is proportional to a differential duty cycle error of the corrected clock signals.  
   
   
       35 . The method of  claim 33  including producing corrected clock signals having a differential duty cycle that converges toward a predetermined value.  
   
   
       36 . The method of  claim 33  including producing corrected clock signals having a differential duty cycle that converges toward about 50%.  
   
   
       37 . The method of  claim 33  including repeatedly producing an offset voltage signal based on the net integrated charge and adjusting a slicing level for the uncorrected clock signals based on the offset voltage.  
   
   
       38 . The method of  claim 33  wherein producing an integrated charge signal includes producing a signal indicative of a time difference between high and low states of the clock signal, wherein the integrated charge signal is proportional to an integrated value of a deviation of the clock signal from a predetermined duty cycle.