Method to form selective cap layers on metal features with narrow spaces

Abstract

Interconnect layers on a semiconductor device containing logic circuits (microprocessors, Asics or others) or random access memory cells (DRAM's) are formed in a manner to significantly reduce the number of shorts between adjacent conductor/vias with narrow separations in technologies having feature sizes of 0.18 microns or smaller. This is accomplished by etching to form recessed copper top surfaces on each layer after a chemical-mechanical polishing process has been completed. The thickness of a selectively formed barrier layer on the recessed copper surfaces, is controlled to be essentially co-planar with the surrounding insulator surfaces. Because the barrier layers are recessed, shorting of adjacent conductive lines is prevented.

1 - 28 . (canceled)  
   
   
       29 . A semiconductor device, comprising: 
 a first insulating layer formed over a substrate, the first insulating layer being patterned with a pattern for at least one conductive line;    a first conductive material disposed within the patterned first insulating layer, the first conductive material being recessed below a top surface of the first insulating layer;    an activation layer disposed over the recessed first conductive material; and    a barrier layer disposed over the activation layer, wherein the activation layer and barrier layer do not extend beyond the top surface of the first insulating layer.    
   
   
       30 . The semiconductor device according to  claim 29 , wherein the first conductive material comprises copper.  
   
   
       31 . The semiconductor device according to  claim 29 , wherein the activation layer comprises Pd.  
   
   
       32 . The semiconductor device according to  claim 29 , wherein the barrier layer comprises CoWP, CoWB, CoP, NiMoP, Re or Ru.  
   
   
       33 . The semiconductor device according to  claim 29 , wherein the first insulating layer comprises a dielectric material with a dielectric constant of 3.7 or less.  
   
   
       34 . The semiconductor device according to  claim 29 , further comprising a liner formed over the patterned first insulating layer.  
   
   
       35 . The semiconductor device according to  claim 34 , wherein forming the liner comprises Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, or a combination thereof.  
   
   
       36 . An integrated circuit chip comprising: 
 a semiconductor device having an electrical contact area;    a first inorganic insulating layer having a relatively high-k formed over the contact area;    a contact via formed completely through the first inorganic insulating layer, the contact via being in contact with the contact area, and the contact via being filled with conductive via material to form a conductive plug that makes electrical contact with the contact area;    a first dielectric layer having a relatively low-k formed over the first inorganic insulating layer;    a first dielectric layer trench formed in a top surface of the first dielectric layer, at least a portion of the first dielectric layer trench opening to the conductive plug;    a first conductive barrier liner layer lining the first dielectric layer trench, at least a portion of the first conductive barrier liner layer being in electrical contact with the conductive plug;    a first conductive material partially fills the first dielectric layer trench such that a first conductive material recess from the top surface of the first dielectric layer is formed in the first dielectric layer trench; and    a first conductive barrier layer formed on a top surface of the first conductive material in the first conductive material recess, the first conductive barrier layer having a top surface that is essentially planar with the top surface of the first dielectric layer.    
   
   
       37 . The chip according to  claim 36 , wherein the first conductive material comprises copper.  
   
   
       38 . The chip according to  claim 36 , further comprising: 
 a second dielectric layer having a relatively low-k and being of the same type as the first dielectric layer formed over the first dielectric layer;    a second dielectric layer trench formed in a top surface of the second dielectric layer, at least a portion of the second dielectric layer trench opening to the first conductive barrier layer;    a second conductive barrier liner layer lining the second dielectric layer trench, at least a portion of the second conductive barrier liner layer being in electrical contact with the first conductive barrier layer;    a second conductive material partially fills the second dielectric layer trench such that a second conductive material recess from the top surface of the second dielectric layer is formed in the second dielectric layer trench; and    a second conductive barrier layer formed on a top surface of the second conductive material in the second conductive material recess, the second conductive barrier layer having a top surface that is essentially planar with the top surface of the second dielectric layer.    
   
   
       39 . The chip according to  claim 38 , further comprising a second inorganic insulating layer having a relatively high-k formed over a top surface of a last of the dielectric layers.  
   
   
       40 . The chip according to  claim 39 , wherein the first and second inorganic insulating layers have a dielectric constant of 3.7 or greater, and wherein the first and second dielectric layers have a dielectric constant of 3.7 or less.  
   
   
       41 . The chip according to  claim 40 , wherein the first and second inorganic layers are each selected from a group consisting of silicon oxide, B-doped oxide (BPSG or BSG), P-doped oxide (BPSG or PSG), and fluorine-doped oxide (FSG).  
   
   
       42 . The chip according to  claim 38 , wherein the second dielectric layer trench comprises a second dielectric layer via extending therefrom and formed in the second dielectric layer, the second dielectric layer via being lined with the same second conductive barrier liner layer used for lining the second dielectric layer trench, and the second dielectric layer via being filled with the same second conductive material used to partially fill the second dielectric layer trench.  
   
   
       43 . The chip according to  claim 36 , wherein the first dielectric layer trench comprises a first dielectric layer via extending therefrom and formed in the first dielectric layer, the first dielectric layer via being lined with the same first conductive barrier liner layer used for lining the first dielectric layer trench, and the first dielectric layer via being filled with the same first conductive material used to partially fill the first dielectric layer trench.  
   
   
       44 . The chip according to  claim 36 , wherein the conductive via material filling the contact via in the first inorganic insulating layer comprises tungsten.  
   
   
       45 . The chip according to  claim 36 , wherein the first conductive barrier liner layer comprises Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, or a combination thereof.  
   
   
       46 . The chip according to  claim 36 , further comprising a conductive activation layer formed in the first conductive material recess over the first conductive material.  
   
   
       47 . The chip according to  claim 46 , wherein the conductive activation layer comprises Pd.  
   
   
       48 . The chip according to  claim 46 , wherein the first conductive barrier layer is formed over the conductive activation layer.  
   
   
       49 . The chip according to  claim 36 , further comprising a conductive activation layer formed in the second conductive material recess over the second conductive material.  
   
   
       50 . The chip according to  claim 49 , wherein the conductive activation layer comprises Pd.  
   
   
       51 . The chip according to  claim 49 , wherein the second conductive barrier layer is formed over the conductive activation layer.  
   
   
       52 . An integrated circuit chip comprising: 
 a semiconductor device having an electrical contact area;    a first dielectric layer formed above the electrical contact area;    a first dielectric layer trench formed in a top surface of the first dielectric layer;    a first conductive barrier liner layer lining the first dielectric layer trench, at least a portion of the first conductive barrier liner layer being electrical connected to the electrical contact area;    a first conductive material partially fills the first dielectric layer trench such that a first conductive material recess from the top surface of the first dielectric layer is formed in the first dielectric layer trench;    a first conductive catalytic activation layer formed in the first conductive material recess over the first conductive material; and    a first conductive barrier layer formed in the first conductive material recess over the first activation layer, the first conductive barrier layer having a top surface that is essentially planar with the top surface of the first dielectric layer.    
   
   
       53 . The chip according to  claim 52 , wherein the first conductive material comprises copper.  
   
   
       54 . The chip according to  claim 52 , further comprising: 
 a second dielectric layer formed over the first dielectric layer;    a second dielectric layer trench formed in a top surface of the second dielectric layer, at least a portion of the second dielectric layer trench opening to the first conductive barrier layer;    a second conductive barrier liner layer lining the second dielectric layer trench, at least a portion of the second conductive barrier liner layer being electrically connected to the first conductive barrier layer;    a second conductive material partially fills the second dielectric layer trench such that a second conductive material recess from the top surface of the second dielectric layer is formed in the second dielectric layer trench;    a second conductive catalytic activation layer formed in the second conductive material recess over the second conductive material; and    a second conductive barrier layer formed in the second conductive material recess over the second activation layer, the second conductive barrier layer having a top surface that is essentially planar with the top surface of the second dielectric layer.    
   
   
       55 . The chip according to  claim 54 , further comprising an inorganic insulating layer formed over a top surface of a last of the dielectric layers.  
   
   
       56 . The chip according to  claim 55 , wherein the inorganic insulating layer has a dielectric constant of 3.7 or greater, and wherein the first and second dielectric layers have a dielectric constant of 3.7 or less.  
   
   
       57 . The chip according to  claim 56 , wherein the inorganic insulating layer comprises a material selected from a group consisting of silicon oxide, B-doped oxide (BPSG or BSG), P-doped oxide (BPSG or PSG), and fluorine-doped oxide (FSG).  
   
   
       58 . The chip according to  claim 54 , wherein the second dielectric layer trench comprises a second dielectric layer via extending therefrom and formed in the second dielectric layer, the second dielectric layer via being lined with the same second conductive barrier liner layer used for lining the second dielectric layer trench, and the second dielectric layer via being filled with the same second conductive material used to partially fill the second dielectric layer trench.  
   
   
       59 . The chip according to  claim 54 , wherein the second activation layer comprises Pd.  
   
   
       60 . The chip according to  claim 52 , further comprising: 
 a first inorganic insulating layer having a relatively high-k formed over the contact area; and    a contact via formed completely through the first inorganic insulating layer, the contact via being in contact with the contact area, and the contact via being filled with conductive via material to form a conductive plug that makes electrical contact with the contact area.    
   
   
       61 . The chip according to  claim 60 , wherein the conductive via material filling the contact via in the first inorganic insulating layer comprises tungsten.  
   
   
       62 . The chip according to  claim 60 , wherein the first inorganic insulating layer has a dielectric constant of 3.7 or greater.  
   
   
       63 . The chip according to  claim 62 , wherein the first inorganic insulating layer comprises a material selected from a group consisting of silicon oxide, B-doped oxide (BPSG or BSG), P-doped oxide (BPSG or PSG), and fluorine-doped oxide (FSG).  
   
   
       64 . The chip according to  claim 52 , wherein the first conductive barrier liner layer comprises Ta, W, Mo, TiW, TiN, TaN, WN, TiSiN, TaSiN, or a combination thereof.  
   
   
       65 . The chip according to  claim 52 , wherein the first activation layer comprises Pd.  
   
   
       66 . The chip according to  claim 52 , wherein the first dielectric layer trench comprises a first dielectric layer via extending therefrom and formed in the first dielectric layer, the first dielectric layer via being lined with the same first conductive barrier liner layer used for lining the first dielectric layer trench, and the first dielectric layer via being filled with the same first conductive material used to partially fill the first dielectric layer trench.