Semiconductor device and method for fabricating the same

Abstract

A semiconductor device includes: a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode; a first interlayer insulating film provided so as to cover the capacitor; a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film; a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect; a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and a passivation layer provided so as to cover the second interconnect.

1 . A semiconductor device, comprising: 
 a capacitor provided on a supporting substrate having an integrated circuit thereon and including a lower electrode, a dielectric film, and an upper electrode;    a first interlayer insulating film provided so as to cover the capacitor;    a first interconnect selectively provided on the first interlayer insulating film and electrically connected to the integrated circuit and the capacitor through a first contact hole formed in the first interlayer insulating film;    a second interlayer insulating film formed of ozone TEOS and provided so as to cover the first interconnect;    a second interconnect selectively provided on the second interlayer insulating film and electrically connected to the first interconnect through a second contact hole formed in the second interlayer insulating film; and    a passivation layer provided so as to cover the second interconnect, wherein the dielectric film is formed from either a dielectric material having a high dielectric constant or a ferroelectric material.    
   
   
       2 . A semiconductor device according to  claim 1 , wherein the second interconnect is provided on the second interlayer insulating film so as to cover at least a part of the capacitor.  
   
   
       3 . A semiconductor device according to  claim 1 , wherein the passivation layer is formed from a laminate including a silicon oxide film and a silicon nitride film.  
   
   
       4 . A semiconductor device according to  claim 1 , further comprising a hydrogen supplying layer provided between the first interconnect and the second interlayer insulating film excluding an area in which the capacitor is provided.  
   
   
       5 . A semiconductor device according to  claim 1 , wherein the first interconnect is formed from a laminate including titanium, titanium nitride, aluminum and titanium nitride; a laminate including titanium, titanium nitride and aluminum; a laminate including titanium, titanium tungsten, aluminum and titanium tungsten; or a laminate including titanium, titanium tungsten and aluminum.  
   
   
       6 . A semiconductor device according to  claim 1 , wherein a Si—OH bond absorption coefficient of the second interlayer insulating film at a wavelength corresponding to 3450 cm −1  is 800 cm −1  or less.  
   
   
       7 . A semiconductor device according to  claim 1 , wherein the second interlayer insulating film has a tensile stress of 1×10 7  dyn/cm 2  to 3×10 9  dyn/cm 2  inclusive.  
   
   
       8 . A semiconductor device according to  claim 1 , wherein the second interlayer insulating film has a thickness of 0.3 μm to 1 μm inclusive.  
   
   
       9 . A semiconductor device according to  claim 1 , wherein the second interconnect is formed from a laminate including titanium, aluminum and titanium nitride; a laminate including titanium and aluminum; or a laminate including titanium, aluminum and titanium tungsten.  
   
   
       10 . A method for fabricating a semiconductor device, comprising the steps of: 
 sequentially forming a lower electrode, a dielectric film, and an upper electrode on a supporting substrate having an integrated circuit, thereby forming a capacitor;    forming a first interlayer insulating film so as to cover the capacitor;    forming a first contact hole in the first interlayer insulating film;    selectively forming a first interconnect in the first contact hole and on a prescribed area of the first interlayer insulating film so as to be electrically connected to the integrated circuit and the capacitor;    forming a second interlayer insulating film of ozone TEOS so as to cover the first interconnect;    subjecting the second interconnect to a first thermal treatment;    forming a second contact hole in the second interlayer insulating film;    selectively forming a second interconnect in the second contact hole and on a prescribed area of the second interlayer insulating film so as to be electrically connected to the first interconnect;    subjecting the second interconnect to a second thermal treatment; and    forming a passivation layer so as to cover the second interconnect, wherein the dielectric film is formed from either a dielectric material having a high dielectric constant or a ferroelectric material.    
   
   
       11 . A method for fabricating a semiconductor device according to  claim 10 , further comprising the step of etching back the second interlayer insulating film using the second interconnect as a mask to such an extent as to almost expose the first interconnect.  
   
   
       12 . A method for fabricating a semiconductor device according to  claim 10 , wherein the step of forming the second interconnect includes the step of forming the second interconnect so as to cover at least a part of the capacitor.  
   
   
       13 . A method for fabricating a semiconductor device according to  claim 10 , wherein: 
 the passivation layer is formed of a laminate including a silicon oxide film and a silicon nitride film, and    the silicon oxide film is formed by normal-pressure CVD, low-pressure CVD or plasma CVD, with using silane, disilane or ozone TEOS, so as to have a tensile stress.    
   
   
       14 . A method for fabricating a semiconductor device according to  claim 10 , further comprising the steps of: 
 after the final interconnect is formed, forming a hydrogen supplying layer on the first interconnect excluding an area where the capacitor is provided; and    performing a third thermal treatment.    
   
   
       15 . A method for fabricating a semiconductor device according to  claim 14 , wherein the hydrogen supplying layer is formed from either silicon nitride or silicon nitride oxide by plasma CVD.  
   
   
       16 . A method for fabricating a semiconductor device according to  claim 14 , wherein the third treatment performed after the formation of hydrogen supplying layer is performed at a temperature in the range of 300° C. to 450° C. inclusive.  
   
   
       17 . A method for fabricating a semiconductor device according to  claim 14 , wherein the third treatment performed after the formation of the hydrogen supplying layer is performed in an oxygen atmosphere, a nitrogen atmosphere, an argon atmosphere or an atmosphere of a mixed gas thereof.  
   
   
       18 . A method for fabricating a semiconductor device according to  claim 10 , wherein the first interlayer insulating film is formed of silicon oxide by normal-pressure CVD or low-pressure CVD, with using silane, disilane or ozone TEOS.  
   
   
       19 . A method for fabricating a semiconductor device according to  claim 10 , wherein the first interlayer insulating film is formed of phosphorous-doped silicon oxide by normal-pressure CVD or low-pressure CVD.  
   
   
       20 . A method for fabricating a semiconductor device according to  claim 10 , wherein an ozone concentration upon forming the second interlayer insulating film using ozone TEOS is set to be at 5.5% or more.  
   
   
       21 . A method for fabricating a semiconductor device according to  claim 10 , wherein the second interlayer insulating film after being subjected with the first thermal treatment has a tensile stress of 1×10 7  dyn/cm 2  to 2×10 9  dyn/cm 2  inclusive.  
   
   
       22 . A method for fabricating a semiconductor device according to  claim 10 , wherein the first thermal treatment is performed at a temperature in the range of 300° C. to 450° C. inclusive.  
   
   
       23 . A method for fabricating a semiconductor device according to  claim 10 , wherein the first thermal treatment is performed in an atmosphere containing at least oxygen.  
   
   
       24 . A method for fabricating a semiconductor device according to  claim 10 , wherein the second thermal treatment is performed at a temperature in the range of 300° C. to 450° C. inclusive.  
   
   
       25 . A method for fabricating a semiconductor device according to  claim 10 , wherein the second thermal treatment is performed in an atmosphere containing at least one of nitrogen, argon an helium.