Embedded capacitor structure in circuit board and method for fabricating the same

Abstract

An embedded capacitor structure in a circuit board and a method for fabricating the same are proposed. The circuit board is formed with a first circuit layer on at least one surface thereof, wherein the first circuit layer has at least one first electrode plate for the capacitor structure. Then, a dielectric layer is formed on the first circuit layer and made flush with the first circuit layer. The dielectric layer has a relatively low dielectric constant and good fluidity to effectively fill the spaces between patterned traces of the first circuit later. A capacitive material is deposited on the dielectric layer and the first circuit layer. Finally, a second circuit layer is formed on the capacitive material and has at least one second electrode plate corresponding to the first electrode plate, together with the capacitive material disposed in-between, to form the capacitor structure.

1 . A method for fabricating an embedded capacitor structure in a circuit board, comprising the steps of: 
 providing the circuit board formed with a first circuit layer on at least one surface thereof, the first circuit layer comprising a plurality of patterned traces;    forming a dielectric layer on the first circuit layer, and thinning the dielectric layer until the patterned traces are exposed;    depositing a capacitive material on the dielectric layer and the first circuit layer; and    forming a second circuit layer on the capacitive material, the second circuit layer comprising a plurality of patterned traces, wherein each of the first and second circuit layers further comprises at least one trace region serving as an electrode plate for the capacitor structure.    
   
   
       2 . The method as recited in  claim 1 , further comprising: forming a build-up structure on the second circuit layer of the circuit board to form a multi-layer circuit board.  
   
   
       3 . The method as recited in  claim 2 , wherein the build-up structure is embedded with at least one capacitor.  
   
   
       4 . The method as recited in  claim 1 , wherein the circuit board is a flip-chip package substrate, wire-bonded package substrate, or printed circuit board.  
   
   
       5 . The method as recited in  claim 1 , wherein the capacitive material is selected from the group consisting of polymers, ceramics, polymers with ceramic powders, and the like.  
   
   
       6 . The method as recited in  claim 1 , wherein the capacitive material is selected from the group consisting of barium titanate, lead zirconate titanate and amorphous hydrogenated carbon, dispersed in a binder.  
   
   
       7 . The method as recited in  claim 1 , wherein the capacitive material is deposited by a sputtering, printing, or roller coating process.  
   
   
       8 . The method as recited in  claim 1 , wherein the dielectric layer is an ajinomoto build-up film (ABF).  
   
   
       9 . The method as recited in  claim 1 , wherein the dielectric layer is made of a material having a lower dielectric constant than that of the capacitive material.  
   
   
       10 . An embedded capacitor structure in a circuit board, comprising: 
 a first circuit layer formed on the circuit board, the first circuit layer comprising a plurality of patterned traces and at least one first electrode plate for the capacitor structure;    a dielectric layer formed on the circuit board and flush with the first circuit layer, wherein the dielectric layer fills spaces between the patterned traces;    a capacitive material deposited on the dielectric layer and the first circuit layer; and    a second circuit layer formed on the capacitive material, and comprising at least one second electrode plate corresponding to the first electrode plate for the capacitor structure.    
   
   
       11 . The embedded capacitor structure as recited in  claim 10 , wherein the capacitive material is selected from the group consisting of polymers, ceramics, polymers with ceramic powders, and the like.  
   
   
       12 . The embedded capacitor structure as recited in  claim 10 , wherein the capacitive material is selected from the group consisting of barium titanate, lead zirconate titanate and amorphous hydrogenated carbon, dispersed in a binder.  
   
   
       13 . The embedded capacitor structure as recited in  claim 10 , wherein the dielectric layer is an ajinomoto build-up film (ABF).  
   
   
       14 . The embedded capacitor structure as recited in  claim 10 , wherein the dielectric layer is made of a material having a lower dielectric constant than that of the capacitive material.  
   
   
       15 . The embedded capacitor structure as recited in  claim 10 , wherein the circuit board is a flip-chip package substrate, wire-bonded package substrate, or printed circuit board.