Selectable delay pulse generator

Abstract

A programmable pulse generator having a clock signal delay chain, multiplexer, and reduced voltage charge circuit. The clock delay chain comprises a plurality of propagated delays, coupled to the multiplexer. The multiplexer selects a particular clock delay signal from a plurality of delay chain taps. The multiplexer is driven by a tap select register coupled to a state machine. The state machine controls the programmable pulse output, encoding the data by varying the pulse width and delay between pulses. The delay of pulse outputs from the multiplexer are reduced by coupling a reduced voltage pre-charge circuit to the multiplexer.

1 . An electronic device for producing a plurality of pulses having a selectable delay between each pulse comprising: 
 a signal delay chain having a plurality of taps;    a plurality of tap select devices coupled to said plurality of taps; and    a tap select register coupled to said plurality of tap select devices, said tap select register configured to selectively couple at least one of said plurality of delay chain taps to a reduced voltage pre-charge circuit.    
   
   
       2 . The electronic device of  claim 1 , wherein said signal delay chain is coupled to a clock signal.  
   
   
       3 . The electronic device of  claim 1 , wherein said signal delay chain is a current controlled delay chain.  
   
   
       4 . The electronic device of  claim 1 , wherein said reduced voltage pre-charge circuit is coupled to a pre-charge control circuit.  
   
   
       5 . The electronic device of  claim 1 , wherein said tap select register is coupled to a state machine.  
   
   
       6 . An electronic device for producing a selectable delay pulse width, said delay between pulses representing encoded data, comprising: 
 a current controlled delay chain, said delay chain having a plurality of taps;    a reduced voltage pre-charge multiplexer coupled to at least one of said plurality of taps; and    a tap select register coupled to said multiplexer, said tap select register configured to couple said delay chain to said multiplexer.    
   
   
       7 . A method for producing an encoded pulse train having a selectable delay between each pulse comprising: 
 applying a clock signal to a delay chain;    selecting at least one delayed clock signal from the delay chain; and    applying a reduced voltage pre-charge signal to the selected delayed block signal, thereby decreasing the output delay time of said selected delayed clock signal.    
   
   
       8 . The method of  claim 7 , wherein said selectable signal delay is a achieved by controlling a current delay chain.  
   
   
       9 . The method of  claim 7 , wherein said selecting a delayed clock signal from the delay chain is performed by a multiplexer.  
   
   
       10 . The method of  claim 9 , further comprising controlling the multiplexer by a register coupled to a state machine.