Integrated circuit package

Abstract

In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate. In another aspect, the invention features an integrated circuit package including a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, a semiconductor die electrically coupled with the conductive via, at least a portion of the semiconductor die being disposed inside the cavity of the substrate, an encapsulant material encapsulating a portion of the semiconductor die such that at least a portion of a surface of the semiconductor die is exposed.

1 - 22 . (canceled)  
   
   
       23 . An integrated circuit package, comprising: 
 a substrate comprising: 
 a first surface,  
 a second surface opposite said first surface,  
 a cavity through said substrate between said first and second surfaces, and  
 a conductive via extending through said substrate and electrically connecting said first surface of said substrate with said second surface of said substrate;  
   a semiconductor die electrically coupled with said conductive via at said first surface of said substrate, at least a portion of said semiconductor die being disposed inside said cavity of said substrate;    an encapsulant material encapsulating a portion of said semiconductor die such that at least a portion of a surface of said semiconductor die is exposed; and    a heat slug thermally and electrically coupled with said semiconductor die, wherein said conductive via is further electrically coupled with said heat slug to provide a ground connection for said semiconductor die at said first surface of said substrate.    
   
   
       24 . The integrated circuit package of  claim 23 , further comprising a conductive member adapted for attachment of said integrated circuit package to an external device.  
   
   
       25 . The integrated circuit package of  claim 24 , said conductive member attached to said first surface of said substrate.  
   
   
       26 . The integrated circuit package of  claim 23 , further comprising at least one wire electrically coupling said semiconductor die with said conductive via.  
   
   
       27 . The integrated circuit package of  claim 23 , at least a portion of said first surface of said substrate being adapted for coupling said integrated circuit package with a second integrated circuit package.  
   
   
       28 . The integrated circuit package of  claim 23 , said substrate further comprising a multi-layer trace embedded therein.  
   
   
       29 . An integrated circuit package assembly comprising the integrated circuit package of  claim 23  attached to at least one other integrated circuit package.  
   
   
       30 . The integrated circuit package assembly of  claim 29 , wherein one of said integrated circuit packages is stacked on top of at least one of the other of said integrated circuit packages.  
   
   
       31 . The integrated circuit package of  claim 25 , further comprising a second conductive member attached to said second surface of said substrate.  
   
   
       32 . The integrated circuit package of  claim 23 , said package having a thickness dimension of about one millimeter.  
   
   
       33 . The integrated circuit package of  claim 39 , said package having a width dimension of about seven millimeters.  
   
   
       34 . The integrated circuit package of  claim 23 , said substrate being substantially planar and said semiconductor die being aligned in a plane with said substrate.  
   
   
       35 . The integrated circuit package of  claim 23 , said integrated circuit package being a land grid array.  
   
   
       36 . The integrated circuit package of  claim 23  said integrated circuit package being a ball grid array.  
   
   
       37 . The integrated circuit package of  claim 23 , said encapsulant material comprising an epoxy.  
   
   
       38 . The integrated circuit package of  claim 23 , further comprising a ring-like trace embedded in said substrate.  
   
   
       39 . The integrated circuit package of  claim 33 , said package having a width dimension of about 7 mm to 50 mm inclusively.  
   
   
       40 . An integrated circuit package, comprising: 
 a substrate comprising: 
 a first surface,  
 a second surface opposite said first surface,  
 a cavity through said substrate between said first and second surfaces, and  
 means for electrically connecting said first surface of said substrate with said second surface of said substrate;  
   a semiconductor die, at least a portion of which is disposed inside said cavity of said substrate;    an encapsulant material encapsulating a portion of said semiconductor die such that at least a portion of a surface of said semiconductor die is exposed; and    means for thermally coupling said semiconductor die to a printed circuit board, wherein said means for thermally coupling is electrically coupled with said means for electrically connecting said first surface of said substrate with said second surface of said substrate to provide a ground connection for said semiconductor die at said first surface of said substrate.    
   
   
       41 . An integrated circuit package assembly comprising the integrated circuit package of  claim 40  attached to at least one other integrated circuit package.  
   
   
       42 . The integrated circuit package assembly of  claim 41 , wherein one of said integrated circuit packages is stacked on top of at least one of the other of said integrated circuit packages.