1T/0C RAM cell with a wrapped-around gate device structure

Abstract

A memory device and a method of forming the memory device. The memory device comprises a storage transistor at a surface of a substrate comprising a body portion between first and second source/drain regions, wherein the source/drain regions are regions of a first conductivity type. The storage transistor also comprises a gate structure that wraps at least partially around the body portion in at least two spatial planes. A bit line is connected to the first source/drain region and a word line connected to the gate structure. The memory device does not require an additional capacitive storage element.

1 . A memory device comprising: 
 a storage transistor at a surface of a substrate, the storage transistor comprising:    a body portion between first and second source/drain regions, wherein the first and second source/drain regions are regions of a first conductivity type, and    a gate structure, wherein the gate structure wraps at least partially around the body portion in at least two spatial planes;    a bit line connected to the first source/drain region; and    a word line connected to the gate structure.    
     
     
         2 . The memory device of  claim 1 , wherein the substrate is a silicon-on-insulator substrate.  
     
     
         3 . The memory device of  claim 1 , wherein the storage transistor is a partially depleted device.  
     
     
         4 . The memory device of  claim 1 , wherein the substrate is a semiconductor layer of a second conductivity type overlying a semiconductor layer of a first conductivity type.  
     
     
         5 . The memory device of  claim 1 , wherein the storage transistor is a FinFET.  
     
     
         6 . The memory device of  claim 1 , wherein the gate structure comprises a gate electrode, and wherein the gate electrode comprises a material from the group consisting of P+ polysilicon, N+ polysilicon, P+ Si x Ge 1-x , N+ Si x Ge 1-x , Ti, TaN, WN, and W.  
     
     
         7 . The memory device of  claim 1 , wherein the gate structure comprises a metal gate electrode.  
     
     
         8 . The memory device of  claim 1 , wherein the body portion contains a heavily doped region of a second conductivity type adjacent to the second source/drain region and separated from the first source/drain region.  
     
     
         9 . The memory device of  claim 1 , wherein the body portion contains an inert dopant region heavily doped with inert ions adjacent to the first source/drain region and separated from the second source/drain region.  
     
     
         10 . The memory device of  claim 1 , wherein the inert dopant region has a dopant dose within the range of approximately 5e12 atoms/cm 2  to approximately 1e16 atoms/cm 2 .  
     
     
         11 . The memory device of  claim 1 , wherein the storage transistor further comprises an insulating layer between the gate structure and the body portion, and wherein the thickness of the insulating layer on a top surface of the body portion is greater than the thickness of the insulating layer on sidewalls of the body portion.  
     
     
         12 . The memory device of  claim 11 , wherein the insulating layer is a material from the group consisting of silicon oxide, oxynitride, nitrided hafnium oxide, aluminum-doped hafnium oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum pentoxide lanthanum oxide, titanium oxide, and yttrium oxide.  
     
     
         13 . The memory device of  claim 11 , wherein the insulating layer is a material having a high dielectric constant.  
     
     
         14 . The memory device of  claim 1 , wherein the storage transistor further comprises a higher Schottky barrier between the second source/drain region and the body portion than a Schottky barrier between the body portion and the first source/drain region.  
     
     
         15 . The memory device of  claim 14 , wherein the storage transistor further comprises a silicide layer in contact with the second source/drain region.  
     
     
         16 . The memory device of  claim 15 , wherein the storage transistor further comprises a silicide layer in contact with the first source/drain region.  
     
     
         17 . The memory device of  claim 1 , wherein the first and second source/drain regions are raised such that the first and second source/drain regions share a same horizontal spatial plane as the portion of the gate structure on a sidewall of the body portion.  
     
     
         18 . The memory device of  claim 1 , wherein the first and second source/drain regions each include a plurality of layers, and wherein the plurality of layers comprises at least one layer of a first material and at least one layer of a second material.  
     
     
         19 . The memory device of  claim 18 , wherein the first and second materials have different band gaps.  
     
     
         20 . The memory device of  claim 18 , wherein the plurality of layers are configured such that a first carrier type gains energy upon moving through the plurality of layers.  
     
     
         21 . The memory device of  claim 18 , wherein the first and second materials have different valence band energies.  
     
     
         22 . The memory device of  claim 18 , wherein the plurality of layers comprises alternating layers of Si x Ge 1-x  and Si y Ge 1-y , respectively, where x is not equal to y.  
     
     
         23 . A dynamic random access memory (DRAM) cell comprising: 
 a storage transistor at a surface of a silicon-on-insulator (SOI) substrate, the storage transistor comprising:    a body portion between first and second source/drain regions, the body portion containing a heavily doped region of a first conductivity type adjacent to the second source/drain region and separated from the first source/drain region, the first and second source/drain regions being regions of a second conductivity type, and    a gate structure, the gate structure wrapping at least partially around the body portion in at least two spatial planes;    a bit line connected to the first source/drain region; and    a word line connected to the gate structure.    
     
     
         24 . The DRAM cell of  claim 23 , wherein the body portion comprises at least one fin-shaped structure, wherein the storage transistor further comprises an oxide layer between the gate structure and the body portion, and wherein the thickness of the oxide layer on a top surface of each fin-shaped structure is greater than the thickness of the oxide layer on sidewalls of each fin-shaped structure.  
     
     
         25 . The DRAM cell of  claim 23 , wherein the first and second source/drain regions are silicided differently from one another.  
     
     
         26 . The memory device of  claim 23 , wherein the first and second source/drain regions have different dopant concentrations than one another.  
     
     
         27 . The DRAM cell of  claim 23 , wherein the body portion comprises an inert dopant region adjacent to the first source/drain region, the inert dopant region having an amorphous dopant profile, and wherein the peak of the dopant profile is within a buried oxide layer.  
     
     
         28 . A memory array comprising: 
 a plurality of memory cells, each memory cell comprising a storage transistor at a surface of a silicon-on-insulator (SOI) substrate, the storage transistor comprising:    a body portion between first and second source/drain regions, the body portion containing a heavily doped region of a first conductivity type adjacent to the second source/drain region and separated from the first source/drain region, the first and second source/drain regions being regions of a second conductivity type, and    a plurality of gates at least partially surrounding the body portion;    a bit line connected to the first source/drain region; and    a word line connected to at least one gate.    
     
     
         29 . The memory array of  claim 28 , wherein the plurality of gates are interconnected.  
     
     
         30 . A semiconductor chip comprising: 
 a plurality of dynamic random access memory (DRAM) cells, at least one DRAM cell comprising a partially depleted storage transistor at a surface of a silicon-on-insulator (SOI) substrate, the storage transistor comprising:    a body portion between first and second source/drain regions, the body portion comprising at least one fin-shaped structure and a region of a first conductivity type adjacent to the second source/drain region, the first and second source/drain regions being regions of a second conductivity type, and    a gate structure, the gate structure wrapping at least partially around each fin-shaped structure;    a bit line connected to the first source/drain region; and    a word line connected to the gate structure.    
     
     
         31 . The semiconductor chip of  claim 30 , wherein the gate structure wraps uninterruptedly around three sides of each fin structure.  
     
     
         32 . A processor system comprising: 
 a processor coupled to a memory device, the memory device comprising a plurality of memory cells, each memory cell comprising a storage transistor at a surface of a substrate, the storage transistor comprising:    a body portion between first and second source/drain regions, the first and second source/drain regions being regions of a first conductivity type, and    a gate structure, the gate structure wrapping at least partially around the body portion in at least two spatial planes;    a bit line connected to the first source/drain region; and    a word line connected to the gate structure.    
     
     
         33 . The processor system of  claim 32 , wherein the substrate is a silicon-on-insulator substrate.  
     
     
         34 . The processor system of  claim 32 , wherein the storage transistor is a FinFET.  
     
     
         35 . The processor system of  claim 32 , wherein the body portion contains a heavily doped region of a second conductivity type adjacent to the second source/drain region and separated from the first source/drain region.  
     
     
         36 . The processor system of  claim 32 , wherein the body portion contains an inert dopant region heavily doped with inert ions adjacent to the first source/drain region and separated from the second source/drain region.  
     
     
         37 . The processor system of  claim 32 , wherein the storage transistor further comprises an oxide layer between the gate structure and the body portion, and wherein the thickness of the oxide layer on a top surface of the body portion is greater than the thickness of the oxide layer on sidewalls of the body portion.  
     
     
         38 . The processor system of  claim 32 , wherein the storage transistor further comprises a higher Schottky barrier between the second source/drain region and the body portion than a Schottky barrier between the body portion and the first source/drain region.  
     
     
         39 . The processor system of  claim 38 , wherein the storage transistor further comprises a silicide layer in contact with the second source/drain region.  
     
     
         40 . The processor system of  claim 39 , wherein the storage transistor further comprises a silicide layer in contact with the first source/drain region.  
     
     
         41 . The processor system of  claim 32 , wherein the first and second source/drain regions are raised such that the first and second source/drain regions share a same horizontal spatial plane as the portion of the gate structure on a sidewall of the body portion.  
     
     
         42 . The processor system of  claim 32 , wherein the first and second source/drain regions each include a plurality of layers, and wherein the plurality of layers comprises at least one layer of a first material and at least one layer of a second material.  
     
     
         43 . The processor system of  claim 42 , wherein the first and second materials have different band gaps.  
     
     
         44 . The processor system of  claim 42 , wherein the plurality of layers are configured such that a first carrier type gains energy upon moving through the plurality of layers.  
     
     
         45 . The processor system of  claim 42 , wherein the first and second materials have different valence band energies.  
     
     
         46 . The processor system of  claim 42 , wherein the plurality of layers comprises alternating layers of Si x Ge 1-x  and Si y Ge 1-y , respectively, where x is not equal to y.  
     
     
         47 . A transistor device comprising: 
 a first source/drain region of a first conductivity type;    a second source/drain region of a first conductivity type;    a body portion for storing charge, the body portion protruding from a surface of a substrate, the body portion being located between the first and second source/drain regions, the body portion including a doped region of a second conductivity type adjacent to the second source/drain region and separated from the first source/drain region; and    a gate structure wrapping around the body portion in at least two spatial planes.    
     
     
         48 . The transistor device of  claim 47 , wherein the substrate is a silicon-on-insulator substrate.  
     
     
         49 . The transistor device of  claim 47 , wherein the substrate is a semiconductor layer of a second conductivity type overlying a semiconductor layer of a first conductivity type.  
     
     
         50 . The transistor device of  claim 47 , wherein the storage transistor is a FinFET.  
     
     
         51 . The transistor device of  claim 47 , wherein the gate structure comprises a gate electrode, and wherein the gate electrode comprises a material from the group consisting of P+ polysilicon, N+ polysilicon, P+ Si x Ge 1-x , N+ Si x Ge 1-x , Ti, TaN, WN, and W.  
     
     
         52 . The transistor device of  claim 47 , wherein the gate structure comprises a metal gate electrode.  
     
     
         53 . The transistor device of  claim 47 , wherein the region of a second conductivity type has an implant dose of between approximately 5e12 atoms/cm 2  to approximately 1e14 atoms/cm 2 .  
     
     
         54 . The transistor device of  claim 47 , wherein the body portion contains an inert dopant region heavily doped with inert ions adjacent to the first source/drain region and separated from the second source/drain region.  
     
     
         55 . The transistor device of  claim 54 , wherein the inert dopant region has a dopant dose within the range of approximately 5e12 atoms/cm 2  to approximately 1e16 atoms/cm 2 .  
     
     
         56 . The transistor device of  claim 47 , further comprising an insulating layer between the gate structure and the body portion, and wherein the thickness of the insulating layer on a top surface of the body portion is greater than the thickness of the insulating layer on sidewalls of the body portion.  
     
     
         57 . The transistor device of  claim 56 , wherein the insulating layer is a material from the group consisting of silicon oxide, oxynitride, nitrided hafnium oxide, aluminum-doped hafnium oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum pentoxide lanthanum oxide, titanium oxide, and yttrium oxide.  
     
     
         58 . The transistor device of  claim 56 , wherein the insulating layer is a material having a high dielectric constant.  
     
     
         59 . The transistor device of  claim 47 , further comprising a higher Schottky barrier between the second source/drain region and the body portion than a Schottky barrier between the body portion and the first source/drain region.  
     
     
         60 . The transistor device of  claim 59 , further comprising a silicide layer in contact with the second source/drain region.  
     
     
         61 . The transistor device of  claim 60 , further comprising a silicide layer in contact with the first source/drain region.  
     
     
         62 . The transistor device of  claim 47 , wherein the first and second source/drain regions are raised such that the first and second source/drain regions share a same horizontal spatial plane as the portion of the gate structure on a sidewall of the body portion.  
     
     
         63 . The transistor device of  claim 47 , wherein the first and second source/drain regions each include a plurality of layers, and wherein the plurality of layers comprises at least one layer of a first material and at least one layer of a second material.  
     
     
         64 . The transistor device of  claim 63 , wherein the first and second materials have different band gaps.  
     
     
         65 . The transistor device of  claim 63 , wherein the plurality of layers are configured such that a first carrier type gains energy upon moving through the plurality of layers.  
     
     
         66 . The transistor device of  claim 63 , wherein the first and second materials have different valence band energies.  
     
     
         67 . The transistor device of  claim 63 , wherein the plurality of layers comprises alternating layers of Si x Ge 1-x  and Si y Ge 1-y , respectively, where x is not equal to y.  
     
     
         68 . A method of forming a memory device, the method comprising: 
 forming a storage transistor at a surface of a substrate, the act of forming the storage transistor comprising:    forming a body portion protruding from a surface of the substrate,    forming a first source/drain region of a first conductivity type on a side of the body portion,    forming a second source/drain region of the first conductivity type on an opposing side of the body portion from the first source/drain region, and    forming a gate structure wrapping at least partially around the body portion in at least two spatial planes;    forming a bit line connected to the first source/drain region; and    forming a word line connected to the gate structure.    
     
     
         69 . The method of  claim 68 , wherein the act of forming the storage transistor comprises forming the storage transistor at a surface of a silicon-on-insulator substrate.  
     
     
         70 . The method of  claim 68 , wherein the act of forming the storage transistor comprises forming a partially depleted storage transistor.  
     
     
         71 . The method of  claim 68 , wherein the act of forming the storage transistor comprises forming the storage transistor at a surface of a semiconductor layer of a second conductivity type and overlying a semiconductor layer of a first conductivity type.  
     
     
         72 . The method of  claim 68 , wherein the act of forming the storage transistor comprises forming a FinFET.  
     
     
         73 . The method of  claim 72 , wherein the act of forming the gate structure comprises forming a gate electrode of a material from the group consisting of P+ polysilicon, N+ polysilicon, P+ Si x Ge 1-x , N+ Si x Ge 1-x , Ti, TaN, WN, and W.  
     
     
         74 . The method of  claim 72 , wherein the act of forming the gate structure comprises forming a metal gate electrode.  
     
     
         75 . The method of  claim 68 , wherein the act of forming the storage transistor further comprises forming a heavily doped region of a second conductivity type adjacent to the second source/drain region and separated from the first source/drain region.  
     
     
         76 . The method of  claim 68 , wherein the act of forming the storage transistor further comprises forming an inert dopant region heavily doped with inert ions adjacent to the first source/drain region and separated from the second source/drain region.  
     
     
         77 . The method of  claim 76 , wherein the act of forming the inert dopant region comprises implanting a dose within the range of approximately 5e12 atoms/cm 2  to approximately 1e16 atoms/cm 2 .  
     
     
         78 . The method of  claim 68 , wherein the act of forming the storage transistor further comprises forming an insulating layer between the gate structure and the body portion, and wherein the thickness of the insulating layer on a top surface of the body portion is greater than the thickness of the insulating layer on a sidewall of the body portion.  
     
     
         79 . The method of  claim 78 , wherein the act of forming the insulating layer comprises forming a layer of a material from the group consisting of silicon oxide, oxynitride, nitrided hafnium oxide, aluminum-doped hafnium oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum pentoxide lanthanum oxide, titanium oxide, and yttrium oxide.  
     
     
         80 . The method of  claim 78 , wherein the act of forming the insulating layer comprises forming a layer of a material having a high dielectric constant.  
     
     
         81 . The method of  claim 68 , wherein the act of forming the storage transistor further comprises forming a higher Schottky barrier between the second source/drain region and the body portion than a Schottky barrier between the body portion and the first source/drain region.  
     
     
         82 . The method of  claim 81 , wherein the act of forming the storage transistor further comprises forming a silicide layer in contact with the second source/drain region.  
     
     
         83 . The method of  claim 82 , wherein the act of forming the storage transistor further comprises forming a silicide layer in contact with the first source/drain region.  
     
     
         84 . The method of  claim 68 , wherein the acts of forming the first and second source/drain regions comprise growing at least one epitaxial layer such that the first and second source/drain regions share a same horizontal spatial plane as the portion of the gate structure on a sidewall of the body portion.  
     
     
         85 . The method of  claim 68 , wherein the acts of forming each of the first and second source/drain regions comprise forming a plurality of layers, the act of forming the plurality of layers comprising forming at least one layer of a first material and at least one layer of a second material.  
     
     
         86 . The memory device of  claim 85 , wherein the first and second materials have different valence band energies.  
     
     
         87 . The method of  claim 85 , wherein the act of forming the plurality of layers comprises forming a plurality of layers having different band gaps.  
     
     
         88 . The method of  claim 85 , wherein the act of forming the plurality of layers comprises configuring the plurality of such that a first carrier type gains energy upon moving through the plurality of layers.  
     
     
         89 . The method of  claim 85 , wherein the act of forming the plurality of layers comprises forming alternating layers of Si x Ge 1-x  and Si y Ge 1-y , where x is not equal to y.  
     
     
         90 . A method of fabricating a storage transistor, the method comprising: 
 forming at least one structure protruding from a surface of the substrate, the at least one structure forming at least a portion of a channel region;    forming a first source/drain region of a first conductivity type on a side of the at least one structure;    forming a second source/drain region of a first conductivity type on a side of the at least one structure opposite to the first source/drain region;    forming a region of a second conductivity type in the substrate adjacent to the second source/drain region and separated from the first source/drain region; and    forming a gate structure, wherein the gate structure wraps at least partially around the at least one fin-shaped structure in at least two spatial planes.    
     
     
         91 . The method of  claim 90 , wherein the act of forming the at least one structure comprises etching a surface of the substrate.  
     
     
         92 . The method of  claim 90 , wherein the act of forming the at least one structure comprises forming the at least one structure protruding from a surface of a silicon-on-insulator substrate.  
     
     
         93 . The method of  claim 90 , wherein the act of forming the at least one structure comprises forming the at least one structure protruding from a surface of a semiconductor layer of a second conductivity type and overlying a semiconductor layer of a first conductivity type.  
     
     
         94 . The method of  claim 90 , wherein the act of forming the at least one structure comprises forming at least on fin-shaped structure.  
     
     
         95 . The method of  claim 90 , wherein the act of forming the gate structure comprises forming a gate electrode of a material from the group consisting of P+ polysilicon, N+ polysilicon, P+Si x Ge 1-x , N+ Si x Ge 1-x , Ti, TaN, WN, and W.  
     
     
         96 . The method of  claim 90 , wherein the act of forming the gate structure comprises forming a metal gate electrode  
     
     
         97 . The method of  claim 90 , further comprising forming an inert dopant region heavily doped with inert ions adjacent to the first source/drain region and separated from the second source/drain region.  
     
     
         98 . The method of  claim 97 , wherein the act of forming the inert dopant region comprises implanting a dose within the range of approximately 5e12 atoms/cm 2  to approximately 1e16 atoms/cm 2 .  
     
     
         99 . The method of  claim 90 , further comprising forming an insulating layer between the gate structure and the body portion, and wherein the thickness of the insulating layer on a top surface of the body portion is greater than the thickness of the insulating layer on a sidewall of the body portion.  
     
     
         100 . The method of  claim 99 , wherein the act of forming the insulating layer comprises forming a layer of a material from the group consisting of silicon oxide, oxynitride, nitrided hafnium oxide, aluminum-doped hafnium oxide, hafnium oxide, aluminum oxide, zirconium oxide, tantalum pentoxide lanthanum oxide, titanium oxide, and yttrium oxide.  
     
     
         101 . The method of  claim 99 , wherein the act of forming the insulating layer comprises forming a layer of a material having a high dielectric constant.  
     
     
         102 . The method of  claim 90 , further comprising forming a higher Schottky barrier between the second source/drain region and the body portion than a Schottky barrier between the body portion and the first source/drain region.  
     
     
         103 . The method of  claim 101 , further comprising forming a silicide layer in contact with the second source/drain region.  
     
     
         104 . The method of  claim 102 , further comprising forming a silicide layer in contact with the first source/drain region.  
     
     
         105 . The method of  claim 90 , wherein the acts of forming the first and second source/drain regions comprise growing at least one epitaxial layer such that the first and second source/drain regions share a same horizontal spatial plane as the portion of the gate structure on a sidewall of the body portion.  
     
     
         106 . The method of  claim 90 , wherein the acts of forming each of the first and second source/drain regions comprise forming a plurality of layers, the act of forming the plurality of layers comprising forming at least one layer of a first material and at least one layer of a second material.  
     
     
         107 . The memory device of  claim 105 , wherein the first and second materials have different valence band energies.  
     
     
         108 . The method of  claim 105 , wherein the first and second materials have different band gaps.  
     
     
         109 . The method of  claim 105 , wherein the act of forming the plurality of layers comprises configuring the plurality of such that a first carrier type gains energy upon moving through the plurality of layers.  
     
     
         110 . The method of  claim 105 , wherein the act of forming the plurality of layers comprises forming alternating layers of Si x Ge 1-x  and Si y Ge 1-y , where x is not equal to y.