Zero latency-zero bus turnaround synchronous flash memory

Abstract

A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. A data buffer is coupled to data communication connections to manage the bi-directional data communication. Finally, a write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. One method of operating a synchronous memory device comprises receiving write data on data connections, latching the write data in a write latch, and releasing the data connections after the write data is latched. A read operation can be performed on the synchronous memory device while the write data is transferred from the write latch to memory cells. Further, the memory device does not require any clock latency during a write operation.

1 . A method of command interleaving in a synchronous memory device comprising: 
 receiving a write command to initiate a write operation; and    receiving a read command to initiate a read operation immediately following receiving the write command.    
     
     
         2 . The method of  claim 1 , further comprising: 
 latching write data in a write latch while receiving the write command; and    performing a write operation to store the write data in the synchronous memory device while receiving the read command.    
     
     
         3 . The method of  claim 1 , wherein the write command sequence comprises: 
 a load command register cycle used to initiate the write operation;    an active cycle used to define and activate a selected row of the memory array; and    a write cycle used to define a column of the memory array and provide write data on the external data connection.    
     
     
         4 . The method of  claim 1 , wherein the data write operation is executed on a first memory bank of the synchronous memory device and the data read operation is executed on a second memory bank.  
     
     
         5 . The method of  claim 1 , wherein the data write operation is executed on a first erase block of the synchronous memory device and the data read operation is executed on a second erase block.  
     
     
         6 . A synchronous memory device, comprising: 
 a memory array arranged in rows and columns;    data communication connections for bi-directional data communication with an external device;    data buffer coupled to the data communication connections to manage the bi-directional data communication; and    a means for latching write data coupled between the data buffer and the memory array to latch write data provided on the data communication connections.    
     
     
         7 . The synchronous memory device of  claim 6 , further comprising control circuitry to copy the data from the means for latching write data to the memory array.  
     
     
         8 . The synchronous memory device of  claim 7 , wherein the memory array is arranged in a plurality of memory blocks, and the control circuitry is configured to copy the data from the means for latching write data to a first block of the plurality of memory blocks.  
     
     
         9 . The synchronous memory device of  claim 8 , wherein the control circuitry is further configured to read data from a second block of the plurality of memory blocks while the data is copied from the means for latching write data to the first block.  
     
     
         10 . The synchronous memory device of  claim 6 , wherein the memory array comprises non-volatile memory cells.  
     
     
         11 . A synchronous memory interface comprising: 
 data communication connections adapted to provide bi-directional data communication with an external communication bus;    data buffer coupled to the data communication connections, wherein the data buffer is adapted to manage the bi-directional data communication and buffer data that is input and/or output from the synchronous memory interface;    a means for latching write data coupled to the data buffer, wherein the means for latching write data is adapted to latch data written to the synchronous memory interface on the data communication connections separate from the data buffer; and    wherein the synchronous memory interface is adapted to receive a read operation and/or transmit read data while a write operation is executed from the means for latching write data.    
     
     
         12 . The synchronous memory interface of  claim 11 , wherein the synchronous memory interface is adapted to receive a write operation command and latch it in the means for latching write data during a wait period of a read operation.  
     
     
         13 . The synchronous memory interface of  claim 12 , wherein the wait period is a read command column address strobe (CAS) latency time period.  
     
     
         14 . The synchronous memory interface of  claim 11 , wherein the synchronous memory interface is adapted to receive a write operation command on the data communication connections and latch the write operation command in the means for latching write data.  
     
     
         15 . The synchronous memory interface of  claim 11 , wherein the synchronous memory interface is adapted to receive a write operation command on a first clock cycle and latch it in the means for latching write data and receive a read command on a second clock cycle, where the second clock cycle immediately follows the first.